example_en_4bit.vh

VHDL examples for counter design, use QuickLogic eclips

module example_en_4bit (
  clear_in,
  clk_in,
  enable_in,
  count_out
);
input clear_in ;
input clk_in ;
input enable_in ;
output [3:0] count_out /* synthesis syn_tristate = 1 */;