example_en_4bit.atr

VHDL examples for counter design, use QuickLogic eclips

I Place .I11.I1 A6
I Fixed .I11.I1 NO
I Place .I11.I2 A5
I Fixed .I11.I2 NO
I Place .I9.QL4 A8
I Fixed .I9.QL4 NO
I Place .I9.QL3 A3
I Fixed .I9.QL3 NO
I Place .I9.QL2 A9
I Fixed .I9.QL2 NO
I Place .I9.QL1 A4
I Fixed .I9.QL1 NO
I Place .I10.I2 A7
I Fixed .I10.I2 NO
I Place .I5.I1 174
I Fixed .I5.I1 NO
I Place .I5.I2 164
I Fixed .I5.I2 NO
I Place .I5.I3 171
I Fixed .I5.I3 NO
I Place .I5.I4 166
I Fixed .I5.I4 NO
I Place .I6 172
I Fixed .I6 NO
I Place .I7 30
I Fixed .I7 NO
I Place .I8 27
I Fixed .I8 NO