example_en_4bit.vq

VHDL examples for counter design, use QuickLogic eclips

`timescale 1ps / 1ps

module example_en_4bit (
  clear_in,
  clk_in,
  enable_in,
  count_out
);
input clear_in ;
input clk_in ;
input enable_in ;
output [3:0] count_out /* synthesis syn_tristate = 1 */;
supply0 GND;
supply1 VCC;
wire qldummy_wire;
wire [3:0] count_reg;
wire [3:0] count;
wire \IO303-OUTMUXZ_ ;
wire \IO303-OUTFF_ ;
wire \IO303-OQQ_ ;
wire \IO303-OUTFFZ_ ;
wire \IO301-OUTMUXZ_ ;
wire \IO301-OUTFF_ ;
wire \IO301-OQQ_ ;
wire \IO301-OUTFFZ_ ;
wire \IO298-INMUXZ_ ;
wire \IO298-VREFZ_ ;
wire \IO298-INPUTZ_ ;
wire \IO290-OUTMUXZ_ ;
wire \IO290-OUTFF_ ;
wire \IO290-OQQ_ ;
wire \IO290-OUTFFZ_ ;
wire \IO288-OUTMUXZ_ ;
wire \IO288-OUTFF_ ;
wire \IO288-OQQ_ ;
wire \IO288-OUTFFZ_ ;
wire \PLLIN0-OP_ ;
wire \PLLIN2-OP_ ;
wire \A9-Q2D_ ;
wire \A9-QCI_ ;
wire \A8-Q2D_ ;
wire \A8-QCI_ ;
wire \A7-Q2D_ ;
wire \A7-QCI_ ;
wire \A6-Q2D_ ;
wire \A6-QCI_ ;
wire \A6-QD_ ;
wire \A6-MC_ ;
wire \A6-O1_ ;
wire \A6-NC_ ;
wire \A6-FI_ ;
wire \A5-Q2D_ ;
wire \A5-QCI_ ;
wire \A5-QD_ ;
wire \A5-MC_ ;
wire \A5-O1_ ;
wire \A5-NC_ ;
wire \A5-FI_ ;
wire \A4-Q2D_ ;
wire \A4-QCI_ ;
wire \A3-Q2D_ ;
wire \A3-QCI_ ;
wire \I11.ED_a ;
wire \I11.BCD_a ;
wire enable;
wire \count_reg[3] ;
wire \count_reg[2] ;
wire \count_reg[1] ;
wire \count_reg[0] ;
wire \count[0] ;
wire \count[1] ;
wire \count[2] ;
wire \count[3] ;
wire enable_reg;
wire clk;
wire clear;

initial
begin
	$display("\nOPERATING RANGE: Commercial");
	$display("\nSPEED GRADE: 6\n");
end

P_SLEWWPD \I5.I3_IO303-FRAG_BSLEW_WPD  (\IO303-OUTMUXZ_ ,VCC,VCC,VCC,
   count_out[2]);
P_MUX2 \I5.I3_IO303-FRAG_BOUT_MUX  (\IO303-OUTFFZ_ ,GND,\count_reg[2] ,GND,VCC,
   \IO303-OUTMUXZ_ );
P_BUF \I5.I3_IO303-FRAG_BOUT_BUF51  (\IO303-OUTFFZ_ ,\IO303-OUTFF_ );
P_BUF \I5.I3_IO303-FRAG_BOUT_BUF  (\IO303-OUTFFZ_ ,\IO303-OQQ_ );
P_FF \I5.I3_IO303-FRAG_BQ_OUT  (\count_reg[2] ,GND,GND,GND,\IO303-OUTFFZ_ );
P_SLEWWPD \I5.I1_IO301-FRAG_BSLEW_WPD  (\IO301-OUTMUXZ_ ,VCC,VCC,VCC,
   count_out[0]);
P_MUX2 \I5.I1_IO301-FRAG_BOUT_MUX  (\IO301-OUTFFZ_ ,GND,\count_reg[0] ,GND,VCC,
   \IO301-OUTMUXZ_ );
P_BUF \I5.I1_IO301-FRAG_BOUT_BUF50  (\IO301-OUTFFZ_ ,\IO301-OUTFF_ );
P_BUF \I5.I1_IO301-FRAG_BOUT_BUF  (\IO301-OUTFFZ_ ,\IO301-OQQ_ );
P_FF \I5.I1_IO301-FRAG_BQ_OUT  (\count_reg[0] ,GND,GND,GND,\IO301-OUTFFZ_ );
P_BUF \I6_IO298-FRAG_BIZ_BUF  (\IO298-INMUXZ_ ,enable);
P_MUX2 \IO298-FRAG_BIN_MUX  (\IO298-VREFZ_ ,GND,\IO298-INPUTZ_ ,GND,VCC,
   \IO298-INMUXZ_ );
P_BUF \IO298-FRAG_BVREF  (\IO298-INPUTZ_ ,\IO298-VREFZ_ );
P_BUF \I6_IO298-FRAG_BIDIR_PAD  (enable_in,\IO298-INPUTZ_ );
P_SLEWWPD \I5.I4_IO290-FRAG_BSLEW_WPD  (\IO290-OUTMUXZ_ ,VCC,VCC,VCC,
   count_out[3]);
P_MUX2 \I5.I4_IO290-FRAG_BOUT_MUX  (\IO290-OUTFFZ_ ,GND,\count_reg[3] ,GND,VCC,
   \IO290-OUTMUXZ_ );
P_BUF \I5.I4_IO290-FRAG_BOUT_BUF49  (\IO290-OUTFFZ_ ,\IO290-OUTFF_ );
P_BUF \I5.I4_IO290-FRAG_BOUT_BUF  (\IO290-OUTFFZ_ ,\IO290-OQQ_ );
P_FF \I5.I4_IO290-FRAG_BQ_OUT  (\count_reg[3] ,GND,GND,GND,\IO290-OUTFFZ_ );
P_SLEWWPD \I5.I2_IO288-FRAG_BSLEW_WPD  (\IO288-OUTMUXZ_ ,VCC,VCC,VCC,
   count_out[1]);
P_MUX2 \I5.I2_IO288-FRAG_BOUT_MUX  (\IO288-OUTFFZ_ ,GND,\count_reg[1] ,GND,VCC,
   \IO288-OUTMUXZ_ );
P_BUF \I5.I2_IO288-FRAG_BOUT_BUF48  (\IO288-OUTFFZ_ ,\IO288-OUTFF_ );
P_BUF \I5.I2_IO288-FRAG_BOUT_BUF  (\IO288-OUTFFZ_ ,\IO288-OQQ_ );
P_FF \I5.I2_IO288-FRAG_BQ_OUT  (\count_reg[1] ,GND,GND,GND,\IO288-OUTFFZ_ );
P_BUF \I7_PLLIN0-FRAG_CLOCK_PLL_BUFF  (clk_in,\PLLIN0-OP_ );
P_BUF \I7_PLLIN0-FRAG_CLOCK_BUFF  (clk_in,clk);
P_BUF \I8_PLLIN2-FRAG_CLOCK_PLL_BUFF  (clear_in,\PLLIN2-OP_ );
P_BUF \I8_PLLIN2-FRAG_CLOCK_BUFF  (clear_in,clear);
P_FF \I9.QL2_A9-FRAG_LQ2  (\A9-Q2D_ ,\A9-QCI_ ,GND,GND,\count_reg[2] );
P_MUX2 \A9-FRAG_LPS  (VCC,GND,\count[2] ,GND,VCC,\A9-Q2D_ );
P_BUF \I9.QL2_A9-FRAG_LQC  (clk,\A9-QCI_ );
P_FF \I9.QL4_A8-FRAG_LQ2  (\A8-Q2D_ ,\A8-QCI_ ,GND,GND,\count_reg[0] );
P_MUX2 \A8-FRAG_LPS  (VCC,GND,\count[0] ,GND,VCC,\A8-Q2D_ );
P_BUF \I9.QL4_A8-FRAG_LQC  (clk,\A8-QCI_ );
P_FF \I10.I2_A7-FRAG_LQ2  (\A7-Q2D_ ,\A7-QCI_ ,GND,GND,enable_reg);
P_MUX2 \A7-FRAG_LPS  (VCC,GND,enable,GND,VCC,\A7-Q2D_ );
P_BUF \I10.I2_A7-FRAG_LQC  (clk,\A7-QCI_ );
P_FF \I11.I1_A6-FRAG_LQ2  (\A6-Q2D_ ,\A6-QCI_ ,GND,clear,\count[2] );
P_MUX2 \I11.I1_A6-FRAG_LPS  (\A6-O1_ ,GND,GND,GND,GND,\A6-Q2D_ );
P_FF \I11.I1_A6-FRAG_LQ  (\A6-QD_ ,\A6-QCI_ ,GND,clear,\count[1] );
P_BUF \I11.I1_A6-FRAG_LQC  (clk,\A6-QCI_ );
P_MUX3 \I11.I1_A6-FRAG_LO  (\I11.ED_a ,\count[1] ,\count[1] ,\I11.ED_a ,
   \A6-MC_ ,GND,\A6-O1_ ,\A6-QD_ );
P_MUX2 \I11.I1_A6-FRAG_LMS  (\count[1] ,GND,\A6-FI_ ,GND,GND,\A6-MC_ );
P_MUX2 \I11.I1_A6-FRAG_LN  (\count[2] ,GND,VCC,\count[2] ,\A6-NC_ ,\A6-O1_ );
P_MUX2 \I11.I1_A6-FRAG_LNS  (GND,GND,\A6-FI_ ,GND,\count[1] ,\A6-NC_ );
P_BUF \I11.I1_A6-FRAG_FB  (\A6-FI_ ,\I11.ED_a );
P_AND6 \I11.I1_A6-FRAG_LF  (enable_reg,GND,\count[0] ,GND,VCC,GND,\A6-FI_ );
P_FF \I11.I2_A5-FRAG_LQ2  (\A5-Q2D_ ,\A5-QCI_ ,GND,clear,\count[0] );
P_MUX2 \I11.I2_A5-FRAG_LPS  (\A5-O1_ ,GND,GND,GND,GND,\A5-Q2D_ );
P_FF \I11.I2_A5-FRAG_LQ  (\A5-QD_ ,\A5-QCI_ ,GND,clear,\count[3] );
P_BUF \I11.I2_A5-FRAG_LQC  (clk,\A5-QCI_ );
P_MUX3 \I11.I2_A5-FRAG_LO  (\count[3] ,GND,VCC,\count[3] ,\A5-MC_ ,GND,
   \A5-O1_ ,\A5-QD_ );
P_MUX2 \I11.I2_A5-FRAG_LMS  (GND,GND,\A5-FI_ ,GND,enable_reg,\A5-MC_ );
P_MUX2 \I11.I2_A5-FRAG_LN  (enable_reg,\count[0] ,\count[0] ,enable_reg,
   \A5-NC_ ,\A5-O1_ );
P_MUX2 \I11.I2_A5-FRAG_LNS  (\count[0] ,GND,\A5-FI_ ,GND,GND,\A5-NC_ );
P_AND6 \I11.I2_A5-FRAG_LF  (\count[2] ,GND,\count[1] ,GND,\count[0] ,GND,
   \A5-FI_ );
P_FF \I9.QL1_A4-FRAG_LQ2  (\A4-Q2D_ ,\A4-QCI_ ,GND,GND,\count_reg[3] );
P_MUX2 \A4-FRAG_LPS  (VCC,GND,\count[3] ,GND,VCC,\A4-Q2D_ );
P_BUF \I9.QL1_A4-FRAG_LQC  (clk,\A4-QCI_ );
P_FF \I9.QL3_A3-FRAG_LQ2  (\A3-Q2D_ ,\A3-QCI_ ,GND,GND,\count_reg[1] );
P_MUX2 \A3-FRAG_LPS  (VCC,GND,\count[1] ,GND,VCC,\A3-Q2D_ );
P_BUF \I9.QL3_A3-FRAG_LQC  (clk,\A3-QCI_ );
endmodule