example_en_4bit.vhh

VHDL examples for counter design, use QuickLogic eclips

entity example_en_4bit is
      Port ( count_out : Out   STD_LOGIC_VECTOR (3 downto 0);
             enable_in : In    STD_LOGIC;
             clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC );
end example_en_4bit;