example_en_4bit.wdl

来自「VHDL examples for counter design, use Qu」· WDL 代码 · 共 11 行

%MASTERCLOCKMULT = 1;
%SMALLESTUNIT    = 9;
%AUTOASSIGN      = 0;
%AUTOEXPORT      = 1;
%DECIMALS        = 0;
%ENDTIME         = 1000000;
clear_in { Z In Default None 0 1 50 } = ; 
clk_in { Z In Default None 0 1 50 } = ; 
count_out[3:0] { Z Out Default None 0 1 50 } = ; 
enable_in { Z In Default None 0 1 50 } = ;