example_en_4bit.qcf

VHDL examples for counter design, use QuickLogic eclips

#QuickLogic Constraint file
#Automatically generated by SpDE version SpDE 9.6.2 Release Build3
#Date: 8/18/2004 at 16:04

#[Part Name]
partname QL8325

#[Package Name]
packname PQ208