📄 ecu_new.vhd
字号:
--------------------------------------------------------------------------------
--
-- File : ecu_new.vhd
-- Last Modification: 12/10/2002
--
-- Created In SpDE Version: SpDE 9.3.2
-- Author : Stanley Hung, QuickLogic Corporation
-- Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind. QuickLogic
-- Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose.
-- In addition and without limiting the generality of the foregoing,
-- QuickLogic does not make any warranty of any kind that any item developed
-- based on this design, or any portion of it, will not infringe any
-- copyright, patent, trade secret or other intellectual property right of
-- any person or entity in any country. It is the responsibility of the user
-- of the design to seek licenses for such intellectual property rights where
-- applicable. QuickLogic shall not be liable for any damages arising out of
-- or in connection with the use of the design including liability for lost
-- profit, business interruption, or any other damages whatsoever.
--
-- Description :
-- ECU macro with reset logic.
--
-- History:
-- Date Author Version
-- 12/10/02 Stanley Hung 1.0
-- - Header added to conform to coding standard.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity RESET_ECU is
Port ( A : In STD_LOGIC_VECTOR (15 downto 0);
B : In STD_LOGIC_VECTOR (15 downto 0);
CIN : In STD_LOGIC;
CLK : In STD_LOGIC;
ecureset : In STD_LOGIC;
S1 : In STD_LOGIC;
S2 : In STD_LOGIC;
S3 : In STD_LOGIC;
A_out : Out STD_LOGIC_VECTOR (15 downto 0);
Bout : Out STD_LOGIC_VECTOR (15 downto 0);
CIN_out : Out STD_LOGIC;
s1_out : Out STD_LOGIC;
s2_out : Out STD_LOGIC;
s3_out : Out STD_LOGIC );
end RESET_ECU;
architecture SCHEMATIC of RESET_ECU is
attribute syn_macro : integer;
attribute ql_pack : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_pack of SCHEMATIC : architecture is 1;
constant VCC : STD_LOGIC := '1';
signal sync_reset_out : STD_LOGIC;
constant GND : STD_LOGIC := '0';
signal sync_reset_rep2 : STD_LOGIC;
signal sync_reset_rep1 : STD_LOGIC;
signal sync_reset_rep5 : STD_LOGIC;
signal sync_reset_rep : STD_LOGIC;
signal sync_reset_rep4 : STD_LOGIC;
signal sync_reset_rep6 : STD_LOGIC;
signal sync_reset : STD_LOGIC;
signal sync_reset_rep3 : STD_LOGIC;
signal A_out_DUMMY : STD_LOGIC_VECTOR (15 downto 0);
signal Bout_DUMMY : STD_LOGIC_VECTOR (15 downto 0);
signal CIN_out_DUMMY : STD_LOGIC;
signal s1_out_DUMMY : STD_LOGIC;
signal s2_out_DUMMY : STD_LOGIC;
signal s3_out_DUMMY : STD_LOGIC;
component MUX2X0
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
S : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component DFF
Port ( CLK : In STD_LOGIC;
D : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component AND2I1
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
begin
A_out(15 downto 0) <= A_out_DUMMY(15 downto 0);
Bout(15 downto 0) <= Bout_DUMMY(15 downto 0);
CIN_out <= CIN_out_DUMMY;
s1_out <= s1_out_DUMMY;
s2_out <= s2_out_DUMMY;
s3_out <= s3_out_DUMMY;
I48 : MUX2X0
Port Map ( A=>S3, B=>VCC, S=>sync_reset_out, Q=>s3_out_DUMMY );
I50 : MUX2X0
Port Map ( A=>S1, B=>VCC, S=>sync_reset_out, Q=>s1_out_DUMMY );
I49 : MUX2X0
Port Map ( A=>S2, B=>VCC, S=>sync_reset_out, Q=>s2_out_DUMMY );
I54 : MUX2X0
Port Map ( A=>A(4), B=>GND, S=>sync_reset, Q=>A_out_DUMMY(4) );
I55 : MUX2X0
Port Map ( A=>B(4), B=>GND, S=>sync_reset_rep3, Q=>Bout_DUMMY(4) );
I38 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep3 );
I39 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep4 );
I51 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_out );
I52 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep5 );
I53 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep6 );
I40 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep1 );
I41 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep2 );
I13 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset_rep );
I12 : DFF
Port Map ( CLK=>CLK, D=>ecureset, Q=>sync_reset );
I42 : AND2I1
Port Map ( A=>CIN, B=>sync_reset_out, Q=>CIN_out_DUMMY );
I33 : AND2I1
Port Map ( A=>A(3), B=>sync_reset, Q=>A_out_DUMMY(3) );
I30 : AND2I1
Port Map ( A=>A(0), B=>sync_reset, Q=>A_out_DUMMY(0) );
I31 : AND2I1
Port Map ( A=>A(1), B=>sync_reset, Q=>A_out_DUMMY(1) );
I32 : AND2I1
Port Map ( A=>A(2), B=>sync_reset, Q=>A_out_DUMMY(2) );
I35 : AND2I1
Port Map ( A=>A(5), B=>sync_reset_rep, Q=>A_out_DUMMY(5) );
I36 : AND2I1
Port Map ( A=>A(6), B=>sync_reset_rep, Q=>A_out_DUMMY(6) );
I37 : AND2I1
Port Map ( A=>A(7), B=>sync_reset_rep, Q=>A_out_DUMMY(7) );
I4 : AND2I1
Port Map ( A=>A(8), B=>sync_reset_rep, Q=>A_out_DUMMY(8) );
I5 : AND2I1
Port Map ( A=>A(9), B=>sync_reset_rep1, Q=>A_out_DUMMY(9) );
I6 : AND2I1
Port Map ( A=>A(10), B=>sync_reset_rep1, Q=>A_out_DUMMY(10) );
I7 : AND2I1
Port Map ( A=>A(11), B=>sync_reset_rep1, Q=>A_out_DUMMY(11) );
I8 : AND2I1
Port Map ( A=>A(12), B=>sync_reset_rep1, Q=>A_out_DUMMY(12) );
I9 : AND2I1
Port Map ( A=>A(13), B=>sync_reset_rep2, Q=>A_out_DUMMY(13) );
I10 : AND2I1
Port Map ( A=>A(14), B=>sync_reset_rep2, Q=>A_out_DUMMY(14) );
I11 : AND2I1
Port Map ( A=>A(15), B=>sync_reset_rep2, Q=>A_out_DUMMY(15) );
I29 : AND2I1
Port Map ( A=>B(15), B=>sync_reset_rep6, Q=>Bout_DUMMY(15) );
I27 : AND2I1
Port Map ( A=>B(13), B=>sync_reset_rep6, Q=>Bout_DUMMY(13) );
I28 : AND2I1
Port Map ( A=>B(14), B=>sync_reset_rep6, Q=>Bout_DUMMY(14) );
I14 : AND2I1
Port Map ( A=>B(0), B=>sync_reset_rep3, Q=>Bout_DUMMY(0) );
I15 : AND2I1
Port Map ( A=>B(1), B=>sync_reset_rep3, Q=>Bout_DUMMY(1) );
I16 : AND2I1
Port Map ( A=>B(2), B=>sync_reset_rep3, Q=>Bout_DUMMY(2) );
I17 : AND2I1
Port Map ( A=>B(3), B=>sync_reset_rep3, Q=>Bout_DUMMY(3) );
I19 : AND2I1
Port Map ( A=>B(5), B=>sync_reset_rep4, Q=>Bout_DUMMY(5) );
I20 : AND2I1
Port Map ( A=>B(6), B=>sync_reset_rep4, Q=>Bout_DUMMY(6) );
I21 : AND2I1
Port Map ( A=>B(7), B=>sync_reset_rep4, Q=>Bout_DUMMY(7) );
I22 : AND2I1
Port Map ( A=>B(8), B=>sync_reset_rep4, Q=>Bout_DUMMY(8) );
I23 : AND2I1
Port Map ( A=>B(9), B=>sync_reset_rep5, Q=>Bout_DUMMY(9) );
I24 : AND2I1
Port Map ( A=>B(10), B=>sync_reset_rep5, Q=>Bout_DUMMY(10) );
I25 : AND2I1
Port Map ( A=>B(11), B=>sync_reset_rep5, Q=>Bout_DUMMY(11) );
I26 : AND2I1
Port Map ( A=>B(12), B=>sync_reset_rep5, Q=>Bout_DUMMY(12) );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity ecu_new is
Port ( A : In STD_LOGIC_VECTOR (15 downto 0);
B : In STD_LOGIC_VECTOR (15 downto 0);
CIN : In STD_LOGIC;
CLK : In STD_LOGIC;
RESET : In STD_LOGIC;
S1 : In STD_LOGIC;
S2 : In STD_LOGIC;
S3 : In STD_LOGIC;
SIGN1 : In STD_LOGIC;
SIGN2 : In STD_LOGIC;
Q : Out STD_LOGIC_VECTOR (16 downto 0) );
end ecu_new;
architecture SCHEMATIC of ecu_new is
signal Bout : STD_LOGIC_VECTOR (15 downto 0);
signal A_out : STD_LOGIC_VECTOR (15 downto 0);
signal ecureset : STD_LOGIC;
signal mode : STD_LOGIC;
constant GND : STD_LOGIC := '0';
signal CIN_out : STD_LOGIC;
signal s1_out : STD_LOGIC;
signal s2_out : STD_LOGIC;
signal s3_out : STD_LOGIC;
signal Q_DUMMY : STD_LOGIC_VECTOR (16 downto 0);
component MUX2X0
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
S : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component AND2I1
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component RESET_ECU
Port ( A : In STD_LOGIC_VECTOR (15 downto 0);
B : In STD_LOGIC_VECTOR (15 downto 0);
CIN : In STD_LOGIC;
CLK : In STD_LOGIC;
ecureset : In STD_LOGIC;
S1 : In STD_LOGIC;
S2 : In STD_LOGIC;
S3 : In STD_LOGIC;
A_out : Out STD_LOGIC_VECTOR (15 downto 0);
Bout : Out STD_LOGIC_VECTOR (15 downto 0);
CIN_out : Out STD_LOGIC;
s1_out : Out STD_LOGIC;
s2_out : Out STD_LOGIC;
s3_out : Out STD_LOGIC );
end component;
component ECU
Port ( A : In STD_LOGIC_VECTOR (15 downto 0);
B : In STD_LOGIC_VECTOR (15 downto 0);
CIN : In STD_LOGIC;
CLK : In STD_LOGIC;
RESET : In STD_LOGIC;
S1 : In STD_LOGIC;
S2 : In STD_LOGIC;
S3 : In STD_LOGIC;
SIGN1 : In STD_LOGIC;
SIGN2 : In STD_LOGIC;
Q : Out STD_LOGIC_VECTOR (16 downto 0) );
end component;
begin
Q(16 downto 0) <= Q_DUMMY(16 downto 0);
I47 : MUX2X0
Port Map ( A=>GND, B=>mode, S=>RESET, Q=>ecureset );
I46 : AND2I1
Port Map ( A=>S2, B=>S3, Q=>mode );
I51 : RESET_ECU
Port Map ( A(15 downto 0)=>A(15 downto 0),
B(15 downto 0)=>B(15 downto 0), CIN=>CIN, CLK=>CLK,
ecureset=>ecureset, S1=>S1, S2=>S2, S3=>S3,
A_out(15 downto 0)=>A_out(15 downto 0),
Bout(15 downto 0)=>Bout(15 downto 0), CIN_out=>CIN_out,
s1_out=>s1_out, s2_out=>s2_out, s3_out=>s3_out );
I3 : ECU
Port Map ( A(15 downto 0)=>A_out(15 downto 0),
B(15 downto 0)=>Bout(15 downto 0), CIN=>CIN_out,
CLK=>CLK, RESET=>GND, S1=>s1_out, S2=>s2_out,
S3=>s3_out, SIGN1=>SIGN1, SIGN2=>SIGN2,
Q(16 downto 0)=>Q_DUMMY(16 downto 0) );
end SCHEMATIC;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -