accum8_25um_new.v

FPGA to design in ECU, very help for engineer

//------------------------------------------------------------------------------
//
// File : accum8_25um_new.v
// Last Modification: 12/10/2002
//
// Created In SpDE Version: SpDE 9.3.2
// Author :	Stanley Hung, QuickLogic Corporation
// Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//
// IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
// This design is provided without warranty of any kind. QuickLogic 
// Corporation does not warrant, guarantee or make any representations
// regarding the use, or the results of the use, of this design. QuickLogic
// disclaims all implied warranties, including but not limited to implied
// warranties of merchantability and fitness for a particular purpose. 
// In addition and without limiting the generality of the foregoing, 
// QuickLogic does not make any warranty of any kind that any item developed 
// based on this design, or any portion of it, will not infringe any 
// copyright, patent, trade secret or other intellectual property right of 
// any person or entity in any country. It is the responsibility of the user
// of the design to seek licenses for such intellectual property rights where
// applicable. QuickLogic shall not be liable for any damages arising out of 
// or in connection with the use of the design including liability for lost
// profit, business interruption, or any other damages whatsoever.
//
// Description :
//	8-bit accumulator macro with reset logic.
//
// History:	
//	Date	        Author					Version
//  12/10/02		Stanley Hung			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 
`include "C:\pasic\spde\data\ecu.v" 

module accum8_25um_new( A , CLK, RESET, Q );
 input [7:0] A;
input CLK;
 output [16:0] Q;
input RESET;
supply0 GND_bit;
wire [7:0] A_out;
supply0 GND;
supply1 VCC;
wire sync_reset_out;

reset_accum8 I5 ( .A({ A[7:0] }), .A_out({ A_out[7:0] }), .CLK(CLK),
               .RESET(RESET), .sync_reset_out(sync_reset_out) );
ECU I3 ( .A({ GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,A_out[7:0] }), .B({ GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,
      GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit,GND_bit }), .CIN(GND), .CLK(CLK),
      .Q({ Q[16:0] }), .RESET(GND), .S1(sync_reset_out), .S2(VCC),
      .S3(sync_reset_out), .SIGN1(GND), .SIGN2(GND) );

endmodule // accum8_25um_new


`ifdef reset_accum8
`else
`define reset_accum8
module reset_accum8( A , CLK, RESET, A_out, sync_reset_out );
 input [7:0] A;
 output [7:0] A_out;
input CLK, RESET;
output sync_reset_out;
parameter syn_macro = 1, ql_pack = 1;
wire sync_reset_rep1;
wire sync_reset;

dff I15 ( .CLK(CLK), .D(RESET), .Q(sync_reset_out) );
dff I13 ( .CLK(CLK), .D(RESET), .Q(sync_reset_rep1) );
dff I14 ( .CLK(CLK), .D(RESET), .Q(sync_reset) );
and2i1 I4 ( .A(A[0]), .B(sync_reset), .Q(A_out[0]) );
and2i1 I5 ( .A(A[1]), .B(sync_reset), .Q(A_out[1]) );
and2i1 I6 ( .A(A[2]), .B(sync_reset), .Q(A_out[2]) );
and2i1 I7 ( .A(A[3]), .B(sync_reset), .Q(A_out[3]) );
and2i1 I8 ( .A(A[4]), .B(sync_reset_rep1), .Q(A_out[4]) );
and2i1 I9 ( .A(A[5]), .B(sync_reset_rep1), .Q(A_out[5]) );
and2i1 I10 ( .A(A[6]), .B(sync_reset_rep1), .Q(A_out[6]) );
and2i1 I11 ( .A(A[7]), .B(sync_reset_rep1), .Q(A_out[7]) );

endmodule // reset_accum8

`endif

`ifdef dff
`else
`define dff
module dff( CLK , D, Q );
input CLK, D;
output Q;
parameter ql_gate = `LOGIC;
supply0 GND;
wire N_1;
supply1 VCC;
wire N_2;
wire N_3;

frag_m I_3 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(D),
          .E2(GND), .NS(N_2), .OS(N_3), .OZ(N_1) );
frag_q I_2 ( .QC(CLK), .QD(N_1), .QR(GND), .QS(GND), .QZ(Q) );
frag_a I_1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_3) );
frag_f QL1 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_2) );

endmodule // dff

`endif

`ifdef and2i1
`else
`define and2i1
module and2i1( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // and2i1

`endif

`ifdef frag_m
`else
`define frag_m
module frag_m( B1 , B2, C1, C2, D1, D2, E1, E2, NS, OS, NZ, OZ );
input B1, B2, C1, C2, D1, D2, E1, E2, NS;
output NZ;
input OS;
output OZ;
parameter ql_frag = 1;
 assign #1 NZ = NS ? (E1 & ~E2):(D1 & ~D2);
 assign #1 OZ = OS ? NZ:(NS ? (C1 & ~C2):(B1 & ~B2));

endmodule // frag_m

`endif

`ifdef frag_q
`else
`define frag_q
module frag_q( QC , QD, QR, QS, QZ );
input QC, QD, QR, QS;
output QZ;
parameter ql_frag = 1;
 reg QZ;
`ifdef synthesis
 always @ (posedge QC or posedge QR or posedge QS) 
     if (QR)
        #1 QZ = 1'b0;
     else if (QS)
        #1 QZ = 1'b1;
     else #1 QZ = QD;
`else
  always @ (QR or QS) begin
      if (QR)
         #1 assign QZ = 1'b0;
      else if (QS)
         #1 assign QZ = 1'b1;
      else
         #1 deassign QZ;
  end
  always @ (posedge QC)
         QZ = #1 QD;
  initial begin
    #1;
    if (QR)
         #1 assign QZ = 1'b0;
    else if (QS)
         #1 assign QZ = 1'b1;
  end
 `endif

endmodule // frag_q

`endif

`ifdef frag_a
`else
`define frag_a
module frag_a( A1 , A2, A3, A4, A5, A6, AZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
parameter ql_frag = 1;
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6;

endmodule // frag_a

`endif

`ifdef frag_f
`else
`define frag_f
module frag_f( F1 , F2, F3, F4, F5, F6, FZ );
input F1, F2, F3, F4, F5, F6;
output FZ;
parameter ql_frag = 1;
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6;

endmodule // frag_f

`endif