accum8_25um_new.vhd

FPGA to design in ECU, very help for engineer

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--
-- File : accum8_25um_new.vhd
-- Last Modification: 12/10/2002
--
-- Created In SpDE Version: SpDE 9.3.2
-- Author :	Stanley Hung, QuickLogic Corporation
-- Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind. QuickLogic 
-- Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose. 
-- In addition and without limiting the generality of the foregoing, 
-- QuickLogic does not make any warranty of any kind that any item developed 
-- based on this design, or any portion of it, will not infringe any 
-- copyright, patent, trade secret or other intellectual property right of 
-- any person or entity in any country. It is the responsibility of the user
-- of the design to seek licenses for such intellectual property rights where
-- applicable. QuickLogic shall not be liable for any damages arising out of 
-- or in connection with the use of the design including liability for lost
-- profit, business interruption, or any other damages whatsoever.
--
-- Description : 
--	8-bit accumulator macro with reset logic.
--
-- History:	
--	Date	        Author					Version
--  12/10/02		Stanley Hung			1.0
--		- Header added to conform to coding standard.
--	
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library IEEE;
use IEEE.std_logic_1164.all;
entity RESET_ACCUM8 is
      Port (       A : In    STD_LOGIC_VECTOR (7 downto 0);
                 CLK : In    STD_LOGIC;
               RESET : In    STD_LOGIC;
               A_out : Out   STD_LOGIC_VECTOR (7 downto 0);
             sync_reset_out : Out   STD_LOGIC );
end RESET_ACCUM8;


architecture SCHEMATIC of RESET_ACCUM8 is

	attribute syn_macro : integer;
	attribute ql_pack   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_pack of SCHEMATIC : architecture is 1;
   signal sync_reset_rep1 : STD_LOGIC;
   signal sync_reset : STD_LOGIC;
   signal A_out_DUMMY : STD_LOGIC_VECTOR  (7 downto 0);
   signal sync_reset_out_DUMMY : STD_LOGIC;

   component DFF
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   A_out(7 downto 0) <= A_out_DUMMY(7 downto 0);
   sync_reset_out <= sync_reset_out_DUMMY;
   I15 : DFF
      Port Map ( CLK=>CLK, D=>RESET, Q=>sync_reset_out_DUMMY );
   I13 : DFF
      Port Map ( CLK=>CLK, D=>RESET, Q=>sync_reset_rep1 );
   I14 : DFF
      Port Map ( CLK=>CLK, D=>RESET, Q=>sync_reset );
   I4 : AND2I1
      Port Map ( A=>A(0), B=>sync_reset, Q=>A_out_DUMMY(0) );
   I5 : AND2I1
      Port Map ( A=>A(1), B=>sync_reset, Q=>A_out_DUMMY(1) );
   I6 : AND2I1
      Port Map ( A=>A(2), B=>sync_reset, Q=>A_out_DUMMY(2) );
   I7 : AND2I1
      Port Map ( A=>A(3), B=>sync_reset, Q=>A_out_DUMMY(3) );
   I8 : AND2I1
      Port Map ( A=>A(4), B=>sync_reset_rep1, Q=>A_out_DUMMY(4) );
   I9 : AND2I1
      Port Map ( A=>A(5), B=>sync_reset_rep1, Q=>A_out_DUMMY(5) );
   I10 : AND2I1
      Port Map ( A=>A(6), B=>sync_reset_rep1, Q=>A_out_DUMMY(6) );
   I11 : AND2I1
      Port Map ( A=>A(7), B=>sync_reset_rep1, Q=>A_out_DUMMY(7) );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
entity accum8_25um_new is
      Port (       A : In    STD_LOGIC_VECTOR (7 downto 0);
                 CLK : In    STD_LOGIC;
               RESET : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR (16 downto 0) );
end accum8_25um_new;


architecture SCHEMATIC of accum8_25um_new is

	constant 		GND_bit : STD_LOGIC := '0';
   signal    A_out : STD_LOGIC_VECTOR (7 downto 0);
	constant 		GND : STD_LOGIC := '0';
	constant 		VCC : STD_LOGIC := '1';
   signal sync_reset_out : STD_LOGIC;
   signal Q_DUMMY : STD_LOGIC_VECTOR  (16 downto 0);

   component RESET_ACCUM8
      Port (       A : In    STD_LOGIC_VECTOR  (7 downto 0);
                 CLK : In    STD_LOGIC;
               RESET : In    STD_LOGIC;
               A_out : Out   STD_LOGIC_VECTOR  (7 downto 0);
             sync_reset_out : Out   STD_LOGIC );
   end component;

   component ECU
      Port (       A : In    STD_LOGIC_VECTOR  (15 downto 0);
                   B : In    STD_LOGIC_VECTOR  (15 downto 0);
                 CIN : In    STD_LOGIC;
                 CLK : In    STD_LOGIC;
               RESET : In    STD_LOGIC;
                  S1 : In    STD_LOGIC;
                  S2 : In    STD_LOGIC;
                  S3 : In    STD_LOGIC;
               SIGN1 : In    STD_LOGIC;
               SIGN2 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (16 downto 0) );
   end component;

begin


   Q(16 downto 0) <= Q_DUMMY(16 downto 0);
   I5 : RESET_ACCUM8
      Port Map ( A(7 downto 0)=>A(7 downto 0), CLK=>CLK, RESET=>RESET,
                 A_out(7 downto 0)=>A_out(7 downto 0),
                 sync_reset_out=>sync_reset_out );
   I3 : ECU
      Port Map (  A(15)=>GND_bit,  A(14)=>GND_bit,  A(13)=>GND_bit,
                  A(12)=>GND_bit,  A(11)=>GND_bit,  A(10)=>GND_bit,
                  A(9)=>GND_bit,  A(8)=>GND_bit,
                 A(7 downto 0)=>A_out(7 downto 0),  B(15)=>GND_bit,
                  B(14)=>GND_bit,  B(13)=>GND_bit,  B(12)=>GND_bit,
                  B(11)=>GND_bit,  B(10)=>GND_bit,  B(9)=>GND_bit,
                  B(8)=>GND_bit,  B(7)=>GND_bit,  B(6)=>GND_bit,
                  B(5)=>GND_bit,  B(4)=>GND_bit,  B(3)=>GND_bit,
                  B(2)=>GND_bit,  B(1)=>GND_bit,  B(0)=>GND_bit,
                 CIN=>gnd, CLK=>CLK, RESET=>gnd, S1=>sync_reset_out,
                 S2=>VCC, S3=>sync_reset_out, SIGN1=>gnd, SIGN2=>gnd,
                 Q(16 downto 0)=>Q_DUMMY(16 downto 0) );

end SCHEMATIC;