clk_gen.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[4\] register cnt\[2\] 379.65 MHz 2.634 ns Internal " "Info: Clock \"clk\" has Internal fmax of 379.65 MHz between source register \"cnt\[4\]\" and destination register \"cnt\[2\]\" (period= 2.634 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.432 ns + Longest register register " "Info: + Longest register to register delay is 2.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[4\] 1 REG LC_X7_Y11_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y11_N7; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[4] } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.454 ns) 1.354 ns Equal0~41 2 COMB LC_X7_Y11_N9 2 " "Info: 2: + IC(0.900 ns) + CELL(0.454 ns) = 1.354 ns; Loc. = LC_X7_Y11_N9; Fanout = 2; COMB Node = 'Equal0~41'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.354 ns" { cnt[4] Equal0~41 } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.238 ns) 2.432 ns cnt\[2\] 3 REG LC_X7_Y11_N6 5 " "Info: 3: + IC(0.840 ns) + CELL(0.238 ns) = 2.432 ns; Loc. = LC_X7_Y11_N6; Fanout = 5; REG Node = 'cnt\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.078 ns" { Equal0~41 cnt[2] } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.692 ns ( 28.45 % ) " "Info: Total cell delay = 0.692 ns ( 28.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.740 ns ( 71.55 % ) " "Info: Total interconnect delay = 1.740 ns ( 71.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.432 ns" { cnt[4] Equal0~41 cnt[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.432 ns" { cnt[4] Equal0~41 cnt[2] } { 0.000ns 0.900ns 0.840ns } { 0.000ns 0.454ns 0.238ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.129 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns cnt\[2\] 2 REG LC_X7_Y11_N6 5 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y11_N6; Fanout = 5; REG Node = 'cnt\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk cnt[2] } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[2] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns cnt\[4\] 2 REG LC_X7_Y11_N7 3 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y11_N7; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk cnt[4] } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[4] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[2] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[4] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.432 ns" { cnt[4] Equal0~41 cnt[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.432 ns" { cnt[4] Equal0~41 cnt[2] } { 0.000ns 0.900ns 0.840ns } { 0.000ns 0.454ns 0.238ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[2] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 cnt[4] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_scan clk_scan~reg0 5.260 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_scan\" through register \"clk_scan~reg0\" is 5.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns clk_scan~reg0 2 REG LC_X6_Y11_N2 1 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X6_Y11_N2; Fanout = 1; REG Node = 'clk_scan~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk clk_scan~reg0 } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk clk_scan~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 clk_scan~reg0 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.958 ns + Longest register pin " "Info: + Longest register to pin delay is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_scan~reg0 1 REG LC_X6_Y11_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y11_N2; Fanout = 1; REG Node = 'clk_scan~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_scan~reg0 } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.324 ns) + CELL(1.634 ns) 2.958 ns clk_scan 2 PIN PIN_4 0 " "Info: 2: + IC(1.324 ns) + CELL(1.634 ns) = 2.958 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'clk_scan'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.958 ns" { clk_scan~reg0 clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 55.24 % ) " "Info: Total cell delay = 1.634 ns ( 55.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns ( 44.76 % ) " "Info: Total interconnect delay = 1.324 ns ( 44.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.958 ns" { clk_scan~reg0 clk_scan } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.958 ns" { clk_scan~reg0 clk_scan } { 0.000ns 1.324ns } { 0.000ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk clk_scan~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 clk_scan~reg0 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.958 ns" { clk_scan~reg0 clk_scan } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.958 ns" { clk_scan~reg0 clk_scan } { 0.000ns 1.324ns } { 0.000ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 27 15:43:07 2008 " "Info: Processing ended: Fri Jun 27 15:43:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}