clk_gen.tan.rpt

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

; Slack ; Actual fmax (period)                           ; From   ; To            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 379.65 MHz ( period = 2.634 ns )               ; cnt[4] ; cnt[2]        ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; 379.65 MHz ( period = 2.634 ns )               ; cnt[4] ; cnt[4]        ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[2] ; cnt[4]        ; clk        ; clk      ; None                        ; None                      ; 2.172 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; cnt[4]        ; clk        ; clk      ; None                        ; None                      ; 2.131 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[1] ; cnt[4]        ; clk        ; clk      ; None                        ; None                      ; 2.052 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[3] ; cnt[4]        ; clk        ; clk      ; None                        ; None                      ; 2.042 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[2] ; cnt[3]        ; clk        ; clk      ; None                        ; None                      ; 2.020 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[2] ; cnt[2]        ; clk        ; clk      ; None                        ; None                      ; 2.000 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; cnt[2]        ; clk        ; clk      ; None                        ; None                      ; 1.990 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; cnt[3]        ; clk        ; clk      ; None                        ; None                      ; 1.979 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[1] ; cnt[2]        ; clk        ; clk      ; None                        ; None                      ; 1.911 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[1] ; cnt[3]        ; clk        ; clk      ; None                        ; None                      ; 1.900 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; cnt[1]        ; clk        ; clk      ; None                        ; None                      ; 1.857 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; clk_scan~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.743 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[3] ; cnt[3]        ; clk        ; clk      ; None                        ; None                      ; 1.495 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[2] ; clk_scan~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.447 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[1] ; cnt[1]        ; clk        ; clk      ; None                        ; None                      ; 1.379 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[3] ; cnt[2]        ; clk        ; clk      ; None                        ; None                      ; 1.369 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[0] ; cnt[0]        ; clk        ; clk      ; None                        ; None                      ; 1.326 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[1] ; clk_scan~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[3] ; clk_scan~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.255 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt[4] ; clk_scan~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.113 ns                ;
+-------+------------------------------------------------+--------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 5.260 ns   ; clk_scan~reg0 ; clk_scan ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 27 15:43:06 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_gen -c clk_gen --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 379.65 MHz between source register "cnt[4]" and destination register "cnt[2]" (period= 2.634 ns)
    Info: + Longest register to register delay is 2.432 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y11_N7; Fanout = 3; REG Node = 'cnt[4]'
        Info: 2: + IC(0.900 ns) + CELL(0.454 ns) = 1.354 ns; Loc. = LC_X7_Y11_N9; Fanout = 2; COMB Node = 'Equal0~41'
        Info: 3: + IC(0.840 ns) + CELL(0.238 ns) = 2.432 ns; Loc. = LC_X7_Y11_N6; Fanout = 5; REG Node = 'cnt[2]'
        Info: Total cell delay = 0.692 ns ( 28.45 % )
        Info: Total interconnect delay = 1.740 ns ( 71.55 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.129 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y11_N6; Fanout = 5; REG Node = 'cnt[2]'
            Info: Total cell delay = 1.677 ns ( 78.77 % )
            Info: Total interconnect delay = 0.452 ns ( 21.23 % )
        Info: - Longest clock path from clock "clk" to source register is 2.129 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y11_N7; Fanout = 3; REG Node = 'cnt[4]'
            Info: Total cell delay = 1.677 ns ( 78.77 % )
            Info: Total interconnect delay = 0.452 ns ( 21.23 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "clk_scan" through register "clk_scan~reg0" is 5.260 ns
    Info: + Longest clock path from clock "clk" to source register is 2.129 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X6_Y11_N2; Fanout = 1; REG Node = 'clk_scan~reg0'
        Info: Total cell delay = 1.677 ns ( 78.77 % )
        Info: Total interconnect delay = 0.452 ns ( 21.23 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.958 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y11_N2; Fanout = 1; REG Node = 'clk_scan~reg0'
        Info: 2: + IC(1.324 ns) + CELL(1.634 ns) = 2.958 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'clk_scan'
        Info: Total cell delay = 1.634 ns ( 55.24 % )
        Info: Total interconnect delay = 1.324 ns ( 44.76 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Fri Jun 27 15:43:07 2008
    Info: Elapsed time: 00:00:01