clk_gen.vhd

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity clk_gen is
port(clk:in std_logic;
     clk_scan:out std_logic);
end clk_gen;

architecture behav of clk_gen is
signal cnt:integer range 0 to 19;
begin
 process(clk)
 begin
   if clk'event and clk='1' then 
     if cnt=cnt'high then
        cnt<=0;
     else cnt<=cnt+1;
     end if;
     if cnt<cnt'high/2 then
       clk_scan<='0';
     else clk_scan<='1';
     end if;
   end if;
 end process;
end behav;