key.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_TSU_RESULT" "keydecoder_deb:inst2\|keyvalue\[0\] keyin\[2\] keyin\[3\] 1.642 ns register " "Info: tsu for register \"keydecoder_deb:inst2\|keyvalue\[0\]\" (data pin = \"keyin\[2\]\", clock pin = \"keyin\[3\]\") is 1.642 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.379 ns + Longest pin register " "Info: + Longest pin to register delay is 8.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[2\] 1 CLK PIN_40 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_40; Fanout = 7; CLK Node = 'keyin\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[2] } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.184 ns) + CELL(0.340 ns) 6.659 ns keydecoder_deb:inst2\|Mux2~629 2 COMB LC_X19_Y12_N1 1 " "Info: 2: + IC(5.184 ns) + CELL(0.340 ns) = 6.659 ns; Loc. = LC_X19_Y12_N1; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux2~629'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.524 ns" { keyin[2] keydecoder_deb:inst2|Mux2~629 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.340 ns) 7.815 ns keydecoder_deb:inst2\|Mux2~630 3 COMB LC_X17_Y12_N7 1 " "Info: 3: + IC(0.816 ns) + CELL(0.340 ns) = 7.815 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux2~630'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { keydecoder_deb:inst2|Mux2~629 keydecoder_deb:inst2|Mux2~630 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.225 ns) 8.379 ns keydecoder_deb:inst2\|keyvalue\[0\] 4 REG LC_X17_Y12_N5 1 " "Info: 4: + IC(0.339 ns) + CELL(0.225 ns) = 8.379 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.040 ns ( 24.35 % ) " "Info: Total cell delay = 2.040 ns ( 24.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.339 ns ( 75.65 % ) " "Info: Total interconnect delay = 6.339 ns ( 75.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.379 ns" { keyin[2] keydecoder_deb:inst2|Mux2~629 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.379 ns" { keyin[2] keyin[2]~out0 keydecoder_deb:inst2|Mux2~629 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 5.184ns 0.816ns 0.339ns } { 0.000ns 1.135ns 0.340ns 0.340ns 0.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.753 ns + " "Info: + Micro setup delay of destination is 0.753 ns" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyin\[3\] destination 7.490 ns - Shortest register " "Info: - Shortest clock path from clock \"keyin\[3\]\" to destination register is 7.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[3\] 1 CLK PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'keyin\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[3] } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.340 ns) 2.407 ns keydecoder_deb:inst2\|Mux6~709 2 COMB LC_X18_Y12_N4 1 " "Info: 2: + IC(0.932 ns) + CELL(0.340 ns) = 2.407 ns; Loc. = LC_X18_Y12_N4; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux6~709'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { keyin[3] keydecoder_deb:inst2|Mux6~709 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.225 ns) 2.969 ns keydecoder_deb:inst2\|Mux6~711 3 COMB LC_X18_Y12_N0 5 " "Info: 3: + IC(0.337 ns) + CELL(0.225 ns) = 2.969 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2\|Mux6~711'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.562 ns" { keydecoder_deb:inst2|Mux6~709 keydecoder_deb:inst2|Mux6~711 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.433 ns) + CELL(0.088 ns) 7.490 ns keydecoder_deb:inst2\|keyvalue\[0\] 4 REG LC_X17_Y12_N5 1 " "Info: 4: + IC(4.433 ns) + CELL(0.088 ns) = 7.490 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.521 ns" { keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.788 ns ( 23.87 % ) " "Info: Total cell delay = 1.788 ns ( 23.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.702 ns ( 76.13 % ) " "Info: Total interconnect delay = 5.702 ns ( 76.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.490 ns" { keyin[3] keydecoder_deb:inst2|Mux6~709 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.490 ns" { keyin[3] keyin[3]~out0 keydecoder_deb:inst2|Mux6~709 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.932ns 0.337ns 4.433ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.379 ns" { keyin[2] keydecoder_deb:inst2|Mux2~629 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.379 ns" { keyin[2] keyin[2]~out0 keydecoder_deb:inst2|Mux2~629 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 5.184ns 0.816ns 0.339ns } { 0.000ns 1.135ns 0.340ns 0.340ns 0.225ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.490 ns" { keyin[3] keydecoder_deb:inst2|Mux6~709 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.490 ns" { keyin[3] keyin[3]~out0 keydecoder_deb:inst2|Mux6~709 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.932ns 0.337ns 4.433ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk keyvalue\[0\] keydecoder_deb:inst2\|keyvalue\[0\] 15.496 ns register " "Info: tco from clock \"clk\" to destination pin \"keyvalue\[0\]\" through register \"keydecoder_deb:inst2\|keyvalue\[0\]\" is 15.496 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.715 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns clk_gen:inst1\|clk_scan 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.720 ns) 5.689 ns keyscan:inst\|keydrv\[2\] 3 REG LC_X19_Y12_N8 6 " "Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst\|keydrv\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.409 ns" { clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] } "NODE_NAME" } } { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.454 ns) 6.757 ns keydecoder_deb:inst2\|Mux6~710 4 COMB LC_X18_Y12_N3 1 " "Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux6~710'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.088 ns) 7.194 ns keydecoder_deb:inst2\|Mux6~711 5 COMB LC_X18_Y12_N0 5 " "Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2\|Mux6~711'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.437 ns" { keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.433 ns) + CELL(0.088 ns) 11.715 ns keydecoder_deb:inst2\|keyvalue\[0\] 6 REG LC_X17_Y12_N5 1 " "Info: 6: + IC(4.433 ns) + CELL(0.088 ns) = 11.715 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.521 ns" { keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 27.32 % ) " "Info: Total cell delay = 3.200 ns ( 27.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.515 ns ( 72.68 % ) " "Info: Total interconnect delay = 8.515 ns ( 72.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.715 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.715 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.433ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.781 ns + Longest register pin " "Info: + Longest register to pin delay is 3.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keydecoder_deb:inst2\|keyvalue\[0\] 1 REG LC_X17_Y12_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.147 ns) + CELL(1.634 ns) 3.781 ns keyvalue\[0\] 2 PIN PIN_3 0 " "Info: 2: + IC(2.147 ns) + CELL(1.634 ns) = 3.781 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'keyvalue\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.781 ns" { keydecoder_deb:inst2|keyvalue[0] keyvalue[0] } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 72 800 976 88 "keyvalue\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 43.22 % ) " "Info: Total cell delay = 1.634 ns ( 43.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.147 ns ( 56.78 % ) " "Info: Total interconnect delay = 2.147 ns ( 56.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.781 ns" { keydecoder_deb:inst2|keyvalue[0] keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.781 ns" { keydecoder_deb:inst2|keyvalue[0] keyvalue[0] } { 0.000ns 2.147ns } { 0.000ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.715 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.715 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.433ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.781 ns" { keydecoder_deb:inst2|keyvalue[0] keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.781 ns" { keydecoder_deb:inst2|keyvalue[0] keyvalue[0] } { 0.000ns 2.147ns } { 0.000ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "keydecoder_deb:inst2\|keyvalue\[1\] keyin\[0\] clk 5.796 ns register " "Info: th for register \"keydecoder_deb:inst2\|keyvalue\[1\]\" (data pin = \"keyin\[0\]\", clock pin = \"clk\") is 5.796 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.714 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns clk_gen:inst1\|clk_scan 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.720 ns) 5.689 ns keyscan:inst\|keydrv\[2\] 3 REG LC_X19_Y12_N8 6 " "Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst\|keydrv\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.409 ns" { clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] } "NODE_NAME" } } { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.454 ns) 6.757 ns keydecoder_deb:inst2\|Mux6~710 4 COMB LC_X18_Y12_N3 1 " "Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux6~710'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.088 ns) 7.194 ns keydecoder_deb:inst2\|Mux6~711 5 COMB LC_X18_Y12_N0 5 " "Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2\|Mux6~711'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.437 ns" { keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.432 ns) + CELL(0.088 ns) 11.714 ns keydecoder_deb:inst2\|keyvalue\[1\] 6 REG LC_X17_Y12_N3 1 " "Info: 6: + IC(4.432 ns) + CELL(0.088 ns) = 11.714 ns; Loc. = LC_X17_Y12_N3; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.520 ns" { keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[1] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 27.32 % ) " "Info: Total cell delay = 3.200 ns ( 27.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.514 ns ( 72.68 % ) " "Info: Total interconnect delay = 8.514 ns ( 72.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.714 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.714 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[1] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.432ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.918 ns - Shortest pin register " "Info: - Shortest pin to register d