📄 key.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register clk_gen:inst1\|cnt\[1\] clk_gen:inst1\|cnt\[4\] 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"clk_gen:inst1\|cnt\[1\]\" and destination register \"clk_gen:inst1\|cnt\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.184 ns + Longest register register " "Info: + Longest register to register delay is 2.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_gen:inst1\|cnt\[1\] 1 REG LC_X9_Y6_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N7; Fanout = 5; REG Node = 'clk_gen:inst1\|cnt\[1\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_gen:inst1|cnt[1] } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.443 ns) 0.865 ns clk_gen:inst1\|Add0~73COUT1 2 COMB LC_X9_Y6_N1 2 " "Info: 2: + IC(0.422 ns) + CELL(0.443 ns) = 0.865 ns; Loc. = LC_X9_Y6_N1; Fanout = 2; COMB Node = 'clk_gen:inst1\|Add0~73COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.865 ns" { clk_gen:inst1|cnt[1] clk_gen:inst1|Add0~73COUT1 } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.927 ns clk_gen:inst1\|Add0~77COUT1 3 COMB LC_X9_Y6_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.927 ns; Loc. = LC_X9_Y6_N2; Fanout = 2; COMB Node = 'clk_gen:inst1\|Add0~77COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { clk_gen:inst1|Add0~73COUT1 clk_gen:inst1|Add0~77COUT1 } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.989 ns clk_gen:inst1\|Add0~79COUT1 4 COMB LC_X9_Y6_N3 1 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.989 ns; Loc. = LC_X9_Y6_N3; Fanout = 1; COMB Node = 'clk_gen:inst1\|Add0~79COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { clk_gen:inst1|Add0~77COUT1 clk_gen:inst1|Add0~79COUT1 } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.457 ns clk_gen:inst1\|Add0~80 5 COMB LC_X9_Y6_N4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.468 ns) = 1.457 ns; Loc. = LC_X9_Y6_N4; Fanout = 1; COMB Node = 'clk_gen:inst1\|Add0~80'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { clk_gen:inst1|Add0~79COUT1 clk_gen:inst1|Add0~80 } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.368 ns) 2.184 ns clk_gen:inst1\|cnt\[4\] 6 REG LC_X9_Y6_N6 3 " "Info: 6: + IC(0.359 ns) + CELL(0.368 ns) = 2.184 ns; Loc. = LC_X9_Y6_N6; Fanout = 3; REG Node = 'clk_gen:inst1\|cnt\[4\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.727 ns" { clk_gen:inst1|Add0~80 clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.403 ns ( 64.24 % ) " "Info: Total cell delay = 1.403 ns ( 64.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.781 ns ( 35.76 % ) " "Info: Total interconnect delay = 0.781 ns ( 35.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.184 ns" { clk_gen:inst1|cnt[1] clk_gen:inst1|Add0~73COUT1 clk_gen:inst1|Add0~77COUT1 clk_gen:inst1|Add0~79COUT1 clk_gen:inst1|Add0~80 clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.184 ns" { clk_gen:inst1|cnt[1] clk_gen:inst1|Add0~73COUT1 clk_gen:inst1|Add0~77COUT1 clk_gen:inst1|Add0~79COUT1 clk_gen:inst1|Add0~80 clk_gen:inst1|cnt[4] } { 0.000ns 0.422ns 0.000ns 0.000ns 0.000ns 0.359ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.368ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.107 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns clk_gen:inst1\|cnt\[4\] 2 REG LC_X9_Y6_N6 3 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y6_N6; Fanout = 3; REG Node = 'clk_gen:inst1\|cnt\[4\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { clk clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[4] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.107 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns clk_gen:inst1\|cnt\[1\] 2 REG LC_X9_Y6_N7 5 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y6_N7; Fanout = 5; REG Node = 'clk_gen:inst1\|cnt\[1\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { clk clk_gen:inst1|cnt[1] } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[1] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[4] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[1] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.184 ns" { clk_gen:inst1|cnt[1] clk_gen:inst1|Add0~73COUT1 clk_gen:inst1|Add0~77COUT1 clk_gen:inst1|Add0~79COUT1 clk_gen:inst1|Add0~80 clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.184 ns" { clk_gen:inst1|cnt[1] clk_gen:inst1|Add0~73COUT1 clk_gen:inst1|Add0~77COUT1 clk_gen:inst1|Add0~79COUT1 clk_gen:inst1|Add0~80 clk_gen:inst1|cnt[4] } { 0.000ns 0.422ns 0.000ns 0.000ns 0.000ns 0.359ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.368ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[4] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk clk_gen:inst1|cnt[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk clk~out0 clk_gen:inst1|cnt[1] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_gen:inst1|cnt[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { clk_gen:inst1|cnt[4] } { } { } "" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 15 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 14 " "Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "keyscan:inst\|keydrv\[0\] keydecoder_deb:inst2\|keyvalue\[0\] clk 4.943 ns " "Info: Found hold time violation between source pin or register \"keyscan:inst\|keydrv\[0\]\" and destination pin or register \"keydecoder_deb:inst2\|keyvalue\[0\]\" for clock \"clk\" (Hold time is 4.943 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.199 ns + Largest " "Info: + Largest clock skew is 6.199 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.715 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns clk_gen:inst1\|clk_scan 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1\|clk_scan'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.720 ns) 5.689 ns keyscan:inst\|keydrv\[2\] 3 REG LC_X19_Y12_N8 6 " "Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst\|keydrv\[2\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.409 ns" { clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] } "NODE_NAME" } } { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.454 ns) 6.757 ns keydecoder_deb:inst2\|Mux6~710 4 COMB LC_X18_Y12_N3 1 " "Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux6~710'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.088 ns) 7.194 ns keydecoder_deb:inst2\|Mux6~711 5 COMB LC_X18_Y12_N0 5 " "Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2\|Mux6~711'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.437 ns" { keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.433 ns) + CELL(0.088 ns) 11.715 ns keydecoder_deb:inst2\|keyvalue\[0\] 6 REG LC_X17_Y12_N5 1 " "Info: 6: + IC(4.433 ns) + CELL(0.088 ns) = 11.715 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.521 ns" { keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 27.32 % ) " "Info: Total cell delay = 3.200 ns ( 27.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.515 ns ( 72.68 % ) " "Info: Total interconnect delay = 8.515 ns ( 72.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.715 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.715 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.433ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.516 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 5.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns clk_gen:inst1\|clk_scan 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1\|clk_scan'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.547 ns) 5.516 ns keyscan:inst\|keydrv\[0\] 3 REG LC_X17_Y12_N6 9 " "Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X17_Y12_N6; Fanout = 9; REG Node = 'keyscan:inst\|keydrv\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.236 ns" { clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } "NODE_NAME" } } { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 43.46 % ) " "Info: Total cell delay = 2.397 ns ( 43.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 56.54 % ) " "Info: Total interconnect delay = 3.119 ns ( 56.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.715 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.715 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.433ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" { } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.083 ns - Shortest register register " "Info: - Shortest register to register delay is 1.083 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyscan:inst\|keydrv\[0\] 1 REG LC_X17_Y12_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N6; Fanout = 9; REG Node = 'keyscan:inst\|keydrv\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyscan:inst|keydrv[0] } "NODE_NAME" } } { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns keydecoder_deb:inst2\|Mux2~627 2 COMB LC_X17_Y12_N6 1 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X17_Y12_N6; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux2~627'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.291 ns" { keyscan:inst|keydrv[0] keydecoder_deb:inst2|Mux2~627 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 0.519 ns keydecoder_deb:inst2\|Mux2~630 3 COMB LC_X17_Y12_N7 1 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 0.519 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux2~630'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { keydecoder_deb:inst2|Mux2~627 keydecoder_deb:inst2|Mux2~630 } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.225 ns) 1.083 ns keydecoder_deb:inst2\|keyvalue\[0\] 4 REG LC_X17_Y12_N5 1 " "Info: 4: + IC(0.339 ns) + CELL(0.225 ns) = 1.083 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.604 ns ( 55.77 % ) " "Info: Total cell delay = 0.604 ns ( 55.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.479 ns ( 44.23 % ) " "Info: Total interconnect delay = 0.479 ns ( 44.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.083 ns" { keyscan:inst|keydrv[0] keydecoder_deb:inst2|Mux2~627 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.083 ns" { keyscan:inst|keydrv[0] keydecoder_deb:inst2|Mux2~627 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.140ns 0.339ns } { 0.000ns 0.291ns 0.088ns 0.225ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.715 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.715 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[2] keydecoder_deb:inst2|Mux6~710 keydecoder_deb:inst2|Mux6~711 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.430ns 2.689ns 0.614ns 0.349ns 4.433ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.454ns 0.088ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { clk clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { clk clk~out0 clk_gen:inst1|clk_scan keyscan:inst|keydrv[0] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.083 ns" { keyscan:inst|keydrv[0] keydecoder_deb:inst2|Mux2~627 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.083 ns" { keyscan:inst|keydrv[0] keydecoder_deb:inst2|Mux2~627 keydecoder_deb:inst2|Mux2~630 keydecoder_deb:inst2|keyvalue[0] } { 0.000ns 0.000ns 0.140ns 0.339ns } { 0.000ns 0.291ns 0.088ns 0.225ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
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