key.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|functionkey " "Warning: Node \"keydecoder_deb:inst2\|functionkey\" is a latch" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|keyvalue\[3\] " "Warning: Node \"keydecoder_deb:inst2\|keyvalue\[3\]\" is a latch" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|keyvalue\[2\] " "Warning: Node \"keydecoder_deb:inst2\|keyvalue\[2\]\" is a latch" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|keyvalue\[1\] " "Warning: Node \"keydecoder_deb:inst2\|keyvalue\[1\]\" is a latch" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|keyvalue\[0\] " "Warning: Node \"keydecoder_deb:inst2\|keyvalue\[0\]\" is a latch" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 88 -24 144 104 "clk" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[2\] " "Info: Assuming node \"keyin\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[0\] " "Info: Assuming node \"keyin\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[3\] " "Info: Assuming node \"keyin\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[1\] " "Info: Assuming node \"keyin\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 24 304 472 40 "keyin\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "keydecoder_deb:inst2\|Mux6~710 " "Info: Detected gated clock \"keydecoder_deb:inst2\|Mux6~710\" as buffer" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keydecoder_deb:inst2\|Mux6~710" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keyscan:inst\|keydrv\[3\] " "Info: Detected ripple clock \"keyscan:inst\|keydrv\[3\]\" as buffer" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyscan:inst\|keydrv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "keydecoder_deb:inst2\|Mux6~709 " "Info: Detected gated clock \"keydecoder_deb:inst2\|Mux6~709\" as buffer" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keydecoder_deb:inst2\|Mux6~709" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keyscan:inst\|keydrv\[0\] " "Info: Detected ripple clock \"keyscan:inst\|keydrv\[0\]\" as buffer" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyscan:inst\|keydrv\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keyscan:inst\|keydrv\[2\] " "Info: Detected ripple clock \"keyscan:inst\|keydrv\[2\]\" as buffer" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyscan:inst\|keydrv\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_gen:inst1\|clk_scan " "Info: Detected ripple clock \"clk_gen:inst1\|clk_scan\" as buffer" {  } { { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 7 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_gen:inst1\|clk_scan" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keyscan:inst\|keydrv\[1\] " "Info: Detected ripple clock \"keyscan:inst\|keydrv\[1\]\" as buffer" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyscan:inst\|keydrv\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}