key.map.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 27 15:53:26 2008 " "Info: Processing started: Fri Jun 27 15:53:26 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off key -c key " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key -c key" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../clk_gen/clk_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../clk_gen/clk_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_gen-behav " "Info: Found design unit 1: clk_gen-behav" {  } { { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Info: Found entity 1: clk_gen" {  } { { "../clk_gen/clk_gen.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/clk_gen/clk_gen.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../keyscan/keyscan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../keyscan/keyscan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keyscan-behav " "Info: Found design unit 1: keyscan-behav" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keyscan " "Info: Found entity 1: keyscan" {  } { { "../keyscan/keyscan.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keyscan/keyscan.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../keydecoder_deb/keydecoder_deb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../keydecoder_deb/keydecoder_deb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keydecoder_deb-behav " "Info: Found design unit 1: keydecoder_deb-behav" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keydecoder_deb " "Info: Found entity 1: keydecoder_deb" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file key.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.bdf" "" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "key " "Info: Elaborating entity \"key\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keydecoder_deb keydecoder_deb:inst2 " "Info: Elaborating entity \"keydecoder_deb\" for hierarchy \"keydecoder_deb:inst2\"" {  } { { "key.bdf" "inst2" { Schematic "D:/altera/70/quartus/work/键盘接口电路/key/key.bdf" { { 48 560 744 176 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "keyvalue keydecoder_deb.vhd(22) " "Warning (10631): VHDL Process Statement warning at keydecoder_deb.vhd(22): inferring latch(es) for signal or variable \"keyvalue\", which holds its previous value in one or more paths through the process" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "temp_pressed keydecoder_deb.vhd(22) " "Warning (10631): VHDL Process Statement warning at keydecoder_deb.vhd(22): inferring latch(es) for signal or variable \"temp_pressed\", which holds its previous value in one or more paths through the process" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "functionkey keydecoder_deb.vhd(22) " "Warning (10631): VHDL Process Statement warning at keydecoder_deb.vhd(22): inferring latch(es) for signal or variable \"functionkey\", which holds its previous value in one or more paths through the process" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q1 keydecoder_deb.vhd(52) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(52): signal \"q1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 keydecoder_deb.vhd(52) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(52): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q3 keydecoder_deb.vhd(52) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(52): signal \"q3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q4 keydecoder_deb.vhd(52) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(52): signal \"q4\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q5 keydecoder_deb.vhd(60) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(60): signal \"q5\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 60 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q6 keydecoder_deb.vhd(60) " "Warning (10492): VHDL Process Statement warning at keydecoder_deb.vhd(60): signal \"q6\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 60 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "functionkey keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"functionkey\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "temp_pressed keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"temp_pressed\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[0\] keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"keyvalue\[0\]\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[1\] keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"keyvalue\[1\]\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[2\] keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"keyvalue\[2\]\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[3\] keydecoder_deb.vhd(22) " "Info (10041): Verilog HDL or VHDL info at keydecoder_deb.vhd(22): inferred latch for \"keyvalue\[3\]\"" {  } { { "../keydecoder_deb/keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}