key.tan.rpt

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

    Warning: Node "keydecoder_deb:inst2|keyvalue[0]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "keyin[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "keyin[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "keyin[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "keyin[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "keydecoder_deb:inst2|Mux6~710" as buffer
    Info: Detected ripple clock "keyscan:inst|keydrv[3]" as buffer
    Info: Detected gated clock "keydecoder_deb:inst2|Mux6~709" as buffer
    Info: Detected ripple clock "keyscan:inst|keydrv[0]" as buffer
    Info: Detected ripple clock "keyscan:inst|keydrv[2]" as buffer
    Info: Detected ripple clock "clk_gen:inst1|clk_scan" as buffer
    Info: Detected ripple clock "keyscan:inst|keydrv[1]" as buffer
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "clk_gen:inst1|cnt[1]" and destination register "clk_gen:inst1|cnt[4]"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.184 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N7; Fanout = 5; REG Node = 'clk_gen:inst1|cnt[1]'
            Info: 2: + IC(0.422 ns) + CELL(0.443 ns) = 0.865 ns; Loc. = LC_X9_Y6_N1; Fanout = 2; COMB Node = 'clk_gen:inst1|Add0~73COUT1'
            Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.927 ns; Loc. = LC_X9_Y6_N2; Fanout = 2; COMB Node = 'clk_gen:inst1|Add0~77COUT1'
            Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.989 ns; Loc. = LC_X9_Y6_N3; Fanout = 1; COMB Node = 'clk_gen:inst1|Add0~79COUT1'
            Info: 5: + IC(0.000 ns) + CELL(0.468 ns) = 1.457 ns; Loc. = LC_X9_Y6_N4; Fanout = 1; COMB Node = 'clk_gen:inst1|Add0~80'
            Info: 6: + IC(0.359 ns) + CELL(0.368 ns) = 2.184 ns; Loc. = LC_X9_Y6_N6; Fanout = 3; REG Node = 'clk_gen:inst1|cnt[4]'
            Info: Total cell delay = 1.403 ns ( 64.24 % )
            Info: Total interconnect delay = 0.781 ns ( 35.76 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.107 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
                Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y6_N6; Fanout = 3; REG Node = 'clk_gen:inst1|cnt[4]'
                Info: Total cell delay = 1.677 ns ( 79.59 % )
                Info: Total interconnect delay = 0.430 ns ( 20.41 % )
            Info: - Longest clock path from clock "clk" to source register is 2.107 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
                Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y6_N7; Fanout = 5; REG Node = 'clk_gen:inst1|cnt[1]'
                Info: Total cell delay = 1.677 ns ( 79.59 % )
                Info: Total interconnect delay = 0.430 ns ( 20.41 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "keyscan:inst|keydrv[0]" and destination pin or register "keydecoder_deb:inst2|keyvalue[0]" for clock "clk" (Hold time is 4.943 ns)
    Info: + Largest clock skew is 6.199 ns
        Info: + Longest clock path from clock "clk" to destination register is 11.715 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1|clk_scan'
            Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst|keydrv[2]'
            Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux6~710'
            Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2|Mux6~711'
            Info: 6: + IC(4.433 ns) + CELL(0.088 ns) = 11.715 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
            Info: Total cell delay = 3.200 ns ( 27.32 % )
            Info: Total interconnect delay = 8.515 ns ( 72.68 % )
        Info: - Shortest clock path from clock "clk" to source register is 5.516 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1|clk_scan'
            Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X17_Y12_N6; Fanout = 9; REG Node = 'keyscan:inst|keydrv[0]'
            Info: Total cell delay = 2.397 ns ( 43.46 % )
            Info: Total interconnect delay = 3.119 ns ( 56.54 % )
    Info: - Micro clock to output delay of source is 0.173 ns
    Info: - Shortest register to register delay is 1.083 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N6; Fanout = 9; REG Node = 'keyscan:inst|keydrv[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X17_Y12_N6; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux2~627'
        Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 0.519 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux2~630'
        Info: 4: + IC(0.339 ns) + CELL(0.225 ns) = 1.083 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
        Info: Total cell delay = 0.604 ns ( 55.77 % )
        Info: Total interconnect delay = 0.479 ns ( 44.23 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "keydecoder_deb:inst2|keyvalue[0]" (data pin = "keyin[2]", clock pin = "keyin[3]") is 1.642 ns
    Info: + Longest pin to register delay is 8.379 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_40; Fanout = 7; CLK Node = 'keyin[2]'
        Info: 2: + IC(5.184 ns) + CELL(0.340 ns) = 6.659 ns; Loc. = LC_X19_Y12_N1; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux2~629'
        Info: 3: + IC(0.816 ns) + CELL(0.340 ns) = 7.815 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux2~630'
        Info: 4: + IC(0.339 ns) + CELL(0.225 ns) = 8.379 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
        Info: Total cell delay = 2.040 ns ( 24.35 % )
        Info: Total interconnect delay = 6.339 ns ( 75.65 % )
    Info: + Micro setup delay of destination is 0.753 ns
    Info: - Shortest clock path from clock "keyin[3]" to destination register is 7.490 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'keyin[3]'
        Info: 2: + IC(0.932 ns) + CELL(0.340 ns) = 2.407 ns; Loc. = LC_X18_Y12_N4; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux6~709'
        Info: 3: + IC(0.337 ns) + CELL(0.225 ns) = 2.969 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2|Mux6~711'
        Info: 4: + IC(4.433 ns) + CELL(0.088 ns) = 7.490 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
        Info: Total cell delay = 1.788 ns ( 23.87 % )
        Info: Total interconnect delay = 5.702 ns ( 76.13 % )
Info: tco from clock "clk" to destination pin "keyvalue[0]" through register "keydecoder_deb:inst2|keyvalue[0]" is 15.496 ns
    Info: + Longest clock path from clock "clk" to source register is 11.715 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1|clk_scan'
        Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst|keydrv[2]'
        Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux6~710'
        Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2|Mux6~711'
        Info: 6: + IC(4.433 ns) + CELL(0.088 ns) = 11.715 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
        Info: Total cell delay = 3.200 ns ( 27.32 % )
        Info: Total interconnect delay = 8.515 ns ( 72.68 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 3.781 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N5; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[0]'
        Info: 2: + IC(2.147 ns) + CELL(1.634 ns) = 3.781 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'keyvalue[0]'
        Info: Total cell delay = 1.634 ns ( 43.22 % )
        Info: Total interconnect delay = 2.147 ns ( 56.78 % )
Info: th for register "keydecoder_deb:inst2|keyvalue[1]" (data pin = "keyin[0]", clock pin = "clk") is 5.796 ns
    Info: + Longest clock path from clock "clk" to destination register is 11.714 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'clk_gen:inst1|clk_scan'
        Info: 3: + IC(2.689 ns) + CELL(0.720 ns) = 5.689 ns; Loc. = LC_X19_Y12_N8; Fanout = 6; REG Node = 'keyscan:inst|keydrv[2]'
        Info: 4: + IC(0.614 ns) + CELL(0.454 ns) = 6.757 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux6~710'
        Info: 5: + IC(0.349 ns) + CELL(0.088 ns) = 7.194 ns; Loc. = LC_X18_Y12_N0; Fanout = 5; COMB Node = 'keydecoder_deb:inst2|Mux6~711'
        Info: 6: + IC(4.432 ns) + CELL(0.088 ns) = 11.714 ns; Loc. = LC_X17_Y12_N3; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[1]'
        Info: Total cell delay = 3.200 ns ( 27.32 % )
        Info: Total interconnect delay = 8.514 ns ( 72.68 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 5.918 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_87; Fanout = 7; CLK Node = 'keyin[0]'
        Info: 2: + IC(3.994 ns) + CELL(0.225 ns) = 5.354 ns; Loc. = LC_X17_Y12_N2; Fanout = 1; COMB Node = 'keydecoder_deb:inst2|Mux3~521'
        Info: 3: + IC(0.339 ns) + CELL(0.225 ns) = 5.918 ns; Loc. = LC_X17_Y12_N3; Fanout = 1; REG Node = 'keydecoder_deb:inst2|keyvalue[1]'
        Info: Total cell delay = 1.585 ns ( 26.78 % )
        Info: Total interconnect delay = 4.333 ns ( 73.22 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Fri Jun 27 15:53:46 2008
    Info: Elapsed time: 00:00:01