key.fit.rpt

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 1           ;
; Mid Slack - Fit Attempt 1                                                      ; -3863       ;
; Internal Atom Count - Fit Attempt 1                                            ; 43          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 43          ;
; LAB Count - Fit Attempt 1                                                      ; 7           ;
; Outputs per Lab - Fit Attempt 1                                                ; 3.286       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 5.286       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.714       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:7         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4;1:3     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:4;1:3     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:4;1:3     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:4;1:3     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:4;1:3     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:7         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:4;1:3     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:4;1:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:4;2:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2;1:4;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:7         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2;1:5     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:5;1:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:5     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:7         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:7         ;
; LEs in Chains - Fit Attempt 1                                                  ; 5           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 1           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016       ;
+--------------------------------------------------------------------------------+-------------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff    ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Early Slack - Fit Attempt 1         ; -4460 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff    ;
; Mid Wire Use - Fit Attempt 1        ; 0     ;
; Mid Slack - Fit Attempt 1           ; -2563 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Late Slack - Fit Attempt 1          ; -2563 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff    ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -1541 ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 1     ;
; Mid Slack - Fit Attempt 1           ; -1808 ;
; Late Slack - Fit Attempt 1          ; -1808 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.046 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 27 15:53:32 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off key -c key
Info: Selected device EP1C3T100C6 for design "key"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 56 of 56 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 11 pins of 11 total pins
    Info: Pin keypressed not assigned to an exact location on the device
    Info: Pin functionkey not assigned to an exact location on the device
    Info: Pin keyvalue[3] not assigned to an exact location on the device
    Info: Pin keyvalue[2] not assigned to an exact location on the device
    Info: Pin keyvalue[1] not assigned to an exact location on the device
    Info: Pin keyvalue[0] not assigned to an exact location on the device
    Info: Pin keyin[0] not assigned to an exact location on the device
    Info: Pin keyin[1] not assigned to an exact location on the device
    Info: Pin keyin[2] not assigned to an exact location on the device
    Info: Pin keyin[3] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Automatically promoted signal "clk_gen:inst1|clk_scan" to use Global clock
Info: Automatically promoted signal "keydecoder_deb:inst2|Mux6~711" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal p