📄 keyscan.fit.rpt
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; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |keyscan ; 9 (9) ; 8 ; 0 ; 0 ; 5 ; 0 ; 1 (1) ; 1 (1) ; 7 (7) ; 0 (0) ; 0 (0) ; |keyscan ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; keydrv[0] ; Output ; -- ; -- ; -- ; -- ;
; keydrv[1] ; Output ; -- ; -- ; -- ; -- ;
; keydrv[2] ; Output ; -- ; -- ; -- ; -- ;
; keydrv[3] ; Output ; -- ; -- ; -- ; -- ;
; clk_scan ; Input ; OFF ; OFF ; -- ; -- ;
+-----------+----------+---------------+---------------+-----------------------+-----+
+---------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; clk_scan ; ; ;
+---------------------+-------------------+---------+
+----------------------------------------------------------------------------------------------------------+
; Control Signals ;
+---------------+--------------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+---------------+--------------+---------+--------------+--------+----------------------+------------------+
; clk_scan ; PIN_10 ; 8 ; Clock ; yes ; Global Clock ; GCLK2 ;
; keydrv[0]~269 ; LC_X1_Y11_N1 ; 4 ; Clock enable ; no ; -- ; -- ;
+---------------+--------------+---------+--------------+--------+----------------------+------------------+
+-------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+----------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+----------+----------+---------+----------------------+------------------+
; clk_scan ; PIN_10 ; 8 ; Global Clock ; GCLK2 ;
+----------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------+----------------+
; Name ; Fan-Out ;
+----------------+----------------+
; state[0] ; 9 ;
; state[1] ; 8 ;
; state[2] ; 7 ;
; state[3] ; 5 ;
; keydrv[0]~269 ; 4 ;
; keydrv[3]~reg0 ; 1 ;
; keydrv[2]~reg0 ; 1 ;
; keydrv[1]~reg0 ; 1 ;
; keydrv[0]~reg0 ; 1 ;
+----------------+----------------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 4 / 8,840 ( < 1 % ) ;
; Direct links ; 1 / 11,506 ( < 1 % ) ;
; Global clocks ; 1 / 8 ( 13 % ) ;
; LAB clocks ; 1 / 156 ( < 1 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 4 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 0 / 7,520 ( 0 % ) ;
+----------------------------+----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 9.00) ; Number of LABs (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 9.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 1.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
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