keyscan.tan.rpt

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; keydrv[1]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.856 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; keydrv[2]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.856 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; keydrv[3]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.856 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; keydrv[0]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.749 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; keydrv[1]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.749 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; keydrv[2]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.749 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; keydrv[3]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.749 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; keydrv[0]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; keydrv[1]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; keydrv[2]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; keydrv[3]~reg0 ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; state[0]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.074 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; state[3]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.074 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; state[1]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.073 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[2] ; state[2]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 1.071 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; state[3]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.972 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; state[1]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.971 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; state[2]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.968 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[0] ; state[0]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.964 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[1] ; state[0]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.885 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[1] ; state[2]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.881 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[1] ; state[3]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.878 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[1] ; state[1]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.876 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; state[0]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.744 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; state[2]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.741 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; state[1]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.736 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; state[3] ; state[3]       ; clk_scan   ; clk_scan ; None                        ; None                      ; 0.729 ns                ;
+-------+------------------------------------------------+----------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 5.299 ns   ; keydrv[3]~reg0 ; keydrv[3] ; clk_scan   ;
; N/A   ; None         ; 5.115 ns   ; keydrv[0]~reg0 ; keydrv[0] ; clk_scan   ;
; N/A   ; None         ; 5.102 ns   ; keydrv[2]~reg0 ; keydrv[2] ; clk_scan   ;
; N/A   ; None         ; 4.812 ns   ; keydrv[1]~reg0 ; keydrv[1] ; clk_scan   ;
+-------+--------------+------------+----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Jun 26 19:00:19 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keyscan -c keyscan --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_scan" is an undefined clock
Info: Clock "clk_scan" Internal fmax is restricted to 405.19 MHz between source register "state[1]" and destination register "keydrv[0]~reg0"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.991 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y11_N7; Fanout = 8; REG Node = 'state[1]'
            Info: 2: + IC(0.519 ns) + CELL(0.454 ns) = 0.973 ns; Loc. = LC_X1_Y11_N1; Fanout = 4; COMB Node = 'keydrv[0]~269'
            Info: 3: + IC(0.351 ns) + CELL(0.667 ns) = 1.991 ns; Loc. = LC_X1_Y11_N8; Fanout = 1; REG Node = 'keydrv[0]~reg0'
            Info: Total cell delay = 1.121 ns ( 56.30 % )
            Info: Total interconnect delay = 0.870 ns ( 43.70 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk_scan" to destination register is 2.129 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clk_scan'
                Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X1_Y11_N8; Fanout = 1; REG Node = 'keydrv[0]~reg0'
                Info: Total cell delay = 1.677 ns ( 78.77 % )
                Info: Total interconnect delay = 0.452 ns ( 21.23 % )
            Info: - Longest clock path from clock "clk_scan" to source register is 2.129 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clk_scan'
                Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X1_Y11_N7; Fanout = 8; REG Node = 'state[1]'
                Info: Total cell delay = 1.677 ns ( 78.77 % )
                Info: Total interconnect delay = 0.452 ns ( 21.23 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk_scan" to destination pin "keydrv[3]" through register "keydrv[3]~reg0" is 5.299 ns
    Info: + Longest clock path from clock "clk_scan" to source register is 2.129 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clk_scan'
        Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X1_Y11_N4; Fanout = 1; REG Node = 'keydrv[3]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.77 % )
        Info: Total interconnect delay = 0.452 ns ( 21.23 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.997 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y11_N4; Fanout = 1; REG Node = 'keydrv[3]~reg0'
        Info: 2: + IC(1.363 ns) + CELL(1.634 ns) = 2.997 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'keydrv[3]'
        Info: Total cell delay = 1.634 ns ( 54.52 % )
        Info: Total interconnect delay = 1.363 ns ( 45.48 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Thu Jun 26 19:00:21 2008
    Info: Elapsed time: 00:00:02