keyscan.vhd

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
entity keyscan is
port(clk_scan:in std_logic;
     keydrv:out std_logic_vector(3 downto 0));
end keyscan;

architecture behav of keyscan is
  constant s0:std_logic_vector(3 downto 0):="1110";
  constant s1:std_logic_vector(3 downto 0):="1101";
  constant s2:std_logic_vector(3 downto 0):="1011";
  constant s3:std_logic_vector(3 downto 0):="0111";
  signal state:std_logic_vector(3 downto 0);
begin
 process(clk_scan)
  begin
   if clk_scan'event and clk_scan='1' then
    case state is
      when s0=>state<=s1;keydrv<=s0;
      when s1=>state<=s2;keydrv<=s1;
      when s2=>state<=s3;keydrv<=s2;
      when s3=>state<=s0;keydrv<=s3;
      when others=>state<=s0;
    end case;
   end if;
  end process;
end behav;