keydecoder_deb.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_TH_RESULT" "keyvalue\[1\]\$latch keyin\[0\] keyin\[3\] 1.899 ns register " "Info: th for register \"keyvalue\[1\]\$latch\" (data pin = \"keyin\[0\]\", clock pin = \"keyin\[3\]\") is 1.899 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyin\[3\] destination 7.600 ns + Longest register " "Info: + Longest clock path from clock \"keyin\[3\]\" to destination register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[3\] 1 CLK PIN_87 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_87; Fanout = 1; CLK Node = 'keyin\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[3] } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(0.454 ns) 2.838 ns Mux6~454 2 COMB LC_X19_Y10_N7 1 " "Info: 2: + IC(1.249 ns) + CELL(0.454 ns) = 2.838 ns; Loc. = LC_X19_Y10_N7; Fanout = 1; COMB Node = 'Mux6~454'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { keyin[3] Mux6~454 } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.225 ns) 3.408 ns Mux6~456 3 COMB LC_X19_Y10_N1 5 " "Info: 3: + IC(0.345 ns) + CELL(0.225 ns) = 3.408 ns; Loc. = LC_X19_Y10_N1; Fanout = 5; COMB Node = 'Mux6~456'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { Mux6~454 Mux6~456 } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.088 ns) 7.600 ns keyvalue\[1\]\$latch 4 REG LC_X19_Y10_N6 1 " "Info: 4: + IC(4.104 ns) + CELL(0.088 ns) = 7.600 ns; Loc. = LC_X19_Y10_N6; Fanout = 1; REG Node = 'keyvalue\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.192 ns" { Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.902 ns ( 25.03 % ) " "Info: Total cell delay = 1.902 ns ( 25.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.698 ns ( 74.97 % ) " "Info: Total interconnect delay = 5.698 ns ( 74.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { keyin[3] Mux6~454 Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { keyin[3] keyin[3]~out0 Mux6~454 Mux6~456 keyvalue[1]$latch } { 0.000ns 0.000ns 1.249ns 0.345ns 4.104ns } { 0.000ns 1.135ns 0.454ns 0.225ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.701 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[0\] 1 CLK PIN_85 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_85; Fanout = 7; CLK Node = 'keyin\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[0] } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.909 ns) + CELL(0.088 ns) 5.132 ns Mux3~514 2 COMB LC_X19_Y10_N4 1 " "Info: 2: + IC(3.909 ns) + CELL(0.088 ns) = 5.132 ns; Loc. = LC_X19_Y10_N4; Fanout = 1; COMB Node = 'Mux3~514'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.997 ns" { keyin[0] Mux3~514 } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.225 ns) 5.701 ns keyvalue\[1\]\$latch 3 REG LC_X19_Y10_N6 1 " "Info: 3: + IC(0.344 ns) + CELL(0.225 ns) = 5.701 ns; Loc. = LC_X19_Y10_N6; Fanout = 1; REG Node = 'keyvalue\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { Mux3~514 keyvalue[1]$latch } "NODE_NAME" } } { "keydecoder_deb.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder_deb/keydecoder_deb.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 25.40 % ) " "Info: Total cell delay = 1.448 ns ( 25.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.253 ns ( 74.60 % ) " "Info: Total interconnect delay = 4.253 ns ( 74.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.701 ns" { keyin[0] Mux3~514 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.701 ns" { keyin[0] keyin[0]~out0 Mux3~514 keyvalue[1]$latch } { 0.000ns 0.000ns 3.909ns 0.344ns } { 0.000ns 1.135ns 0.088ns 0.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { keyin[3] Mux6~454 Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { keyin[3] keyin[3]~out0 Mux6~454 Mux6~456 keyvalue[1]$latch } { 0.000ns 0.000ns 1.249ns 0.345ns 4.104ns } { 0.000ns 1.135ns 0.454ns 0.225ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.701 ns" { keyin[0] Mux3~514 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.701 ns" { keyin[0] keyin[0]~out0 Mux3~514 keyvalue[1]$latch } { 0.000ns 0.000ns 3.909ns 0.344ns } { 0.000ns 1.135ns 0.088ns 0.225ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 27 15:12:07 2008 " "Info: Processing ended: Fri Jun 27 15:12:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}