keydecoder.map.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 26 19:41:01 2008 " "Info: Processing started: Thu Jun 26 19:41:01 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off keydecoder -c keydecoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keydecoder -c keydecoder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keydecoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keydecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keydecoder-behav " "Info: Found design unit 1: keydecoder-behav" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keydecoder " "Info: Found entity 1: keydecoder" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "keydecoder " "Info: Elaborating entity \"keydecoder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "keyvalue keydecoder.vhd(20) " "Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable \"keyvalue\", which holds its previous value in one or more paths through the process" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "temp_pressed keydecoder.vhd(20) " "Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable \"temp_pressed\", which holds its previous value in one or more paths through the process" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "functionkey keydecoder.vhd(20) " "Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable \"functionkey\", which holds its previous value in one or more paths through the process" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q1 keydecoder.vhd(48) " "Warning (10492): VHDL Process Statement warning at keydecoder.vhd(48): signal \"q1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 keydecoder.vhd(48) " "Warning (10492): VHDL Process Statement warning at keydecoder.vhd(48): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "functionkey keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"functionkey\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "temp_pressed keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"temp_pressed\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[0\] keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"keyvalue\[0\]\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[1\] keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"keyvalue\[1\]\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[2\] keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"keyvalue\[2\]\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "keyvalue\[3\] keydecoder.vhd(20) " "Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for \"keyvalue\[3\]\"" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "q1 High " "Info: Power-up level of register \"q1\" is not specified -- using power-up level of High to minimize register" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 17 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "q1 data_in VCC " "Warning: Reduced register \"q1\" with stuck data_in port to stuck value VCC" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "q2 High " "Info: Power-up level of register \"q2\" is not specified -- using power-up level of High to minimize register" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 17 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "q2 data_in VCC " "Warning: Reduced register \"q2\" with stuck data_in port to stuck value VCC" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyvalue\[0\]\$latch " "Warning: Latch keyvalue\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA keydrv\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal keydrv\[1\]" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyvalue\[1\]\$latch " "Warning: Latch keyvalue\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA keyin\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal keyin\[0\]" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyvalue\[2\]\$latch " "Warning: Latch keyvalue\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA keydrv\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal keydrv\[2\]" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyvalue\[3\]\$latch " "Warning: Latch keyvalue\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA keydrv\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal keydrv\[0\]" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "functionkey\$latch " "Warning: Latch functionkey\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA keydrv\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal keydrv\[1\]" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "keypressed GND " "Warning: Pin \"keypressed\" stuck at GND" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 19:41:04 2008 " "Info: Processing ended: Thu Jun 26 19:41:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}