keydecoder.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_TH_RESULT" "keyvalue\[0\]\$latch keydrv\[2\] keyin\[1\] 2.511 ns register " "Info: th for register \"keyvalue\[0\]\$latch\" (data pin = \"keydrv\[2\]\", clock pin = \"keyin\[1\]\") is 2.511 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyin\[1\] destination 8.210 ns + Longest register " "Info: + Longest clock path from clock \"keyin\[1\]\" to destination register is 8.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[1\] 1 CLK PIN_39 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_39; Fanout = 7; CLK Node = 'keyin\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[1] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.340 ns) 3.126 ns Mux6~454 2 COMB LC_X16_Y12_N9 1 " "Info: 2: + IC(1.651 ns) + CELL(0.340 ns) = 3.126 ns; Loc. = LC_X16_Y12_N9; Fanout = 1; COMB Node = 'Mux6~454'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.991 ns" { keyin[1] Mux6~454 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.225 ns) 3.695 ns Mux6~456 3 COMB LC_X16_Y12_N1 5 " "Info: 3: + IC(0.344 ns) + CELL(0.225 ns) = 3.695 ns; Loc. = LC_X16_Y12_N1; Fanout = 5; COMB Node = 'Mux6~456'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { Mux6~454 Mux6~456 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.427 ns) + CELL(0.088 ns) 8.210 ns keyvalue\[0\]\$latch 4 REG LC_X16_Y12_N5 1 " "Info: 4: + IC(4.427 ns) + CELL(0.088 ns) = 8.210 ns; Loc. = LC_X16_Y12_N5; Fanout = 1; REG Node = 'keyvalue\[0\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.515 ns" { Mux6~456 keyvalue[0]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.788 ns ( 21.78 % ) " "Info: Total cell delay = 1.788 ns ( 21.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.422 ns ( 78.22 % ) " "Info: Total interconnect delay = 6.422 ns ( 78.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.210 ns" { keyin[1] Mux6~454 Mux6~456 keyvalue[0]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.210 ns" { keyin[1] keyin[1]~out0 Mux6~454 Mux6~456 keyvalue[0]$latch } { 0.000ns 0.000ns 1.651ns 0.344ns 4.427ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.699 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keydrv\[2\] 1 CLK PIN_88 6 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 6; CLK Node = 'keydrv\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keydrv[2] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.905 ns) + CELL(0.088 ns) 5.128 ns Mux2~595 2 COMB LC_X16_Y12_N2 1 " "Info: 2: + IC(3.905 ns) + CELL(0.088 ns) = 5.128 ns; Loc. = LC_X16_Y12_N2; Fanout = 1; COMB Node = 'Mux2~595'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.993 ns" { keydrv[2] Mux2~595 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.346 ns) + CELL(0.225 ns) 5.699 ns keyvalue\[0\]\$latch 3 REG LC_X16_Y12_N5 1 " "Info: 3: + IC(0.346 ns) + CELL(0.225 ns) = 5.699 ns; Loc. = LC_X16_Y12_N5; Fanout = 1; REG Node = 'keyvalue\[0\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { Mux2~595 keyvalue[0]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 25.41 % ) " "Info: Total cell delay = 1.448 ns ( 25.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.251 ns ( 74.59 % ) " "Info: Total interconnect delay = 4.251 ns ( 74.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.699 ns" { keydrv[2] Mux2~595 keyvalue[0]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.699 ns" { keydrv[2] keydrv[2]~out0 Mux2~595 keyvalue[0]$latch } { 0.000ns 0.000ns 3.905ns 0.346ns } { 0.000ns 1.135ns 0.088ns 0.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.210 ns" { keyin[1] Mux6~454 Mux6~456 keyvalue[0]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.210 ns" { keyin[1] keyin[1]~out0 Mux6~454 Mux6~456 keyvalue[0]$latch } { 0.000ns 0.000ns 1.651ns 0.344ns 4.427ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.699 ns" { keydrv[2] Mux2~595 keyvalue[0]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.699 ns" { keydrv[2] keydrv[2]~out0 Mux2~595 keyvalue[0]$latch } { 0.000ns 0.000ns 3.905ns 0.346ns } { 0.000ns 1.135ns 0.088ns 0.225ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 26 19:41:24 2008 " "Info: Processing ended: Thu Jun 26 19:41:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}