keydecoder.tan.qmsg

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keydrv\[1\] " "Info: Assuming node \"keydrv\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keydrv\[2\] " "Info: Assuming node \"keydrv\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keydrv\[3\] " "Info: Assuming node \"keydrv\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keydrv\[0\] " "Info: Assuming node \"keydrv\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[2\] " "Info: Assuming node \"keyin\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[3\] " "Info: Assuming node \"keyin\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[1\] " "Info: Assuming node \"keyin\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "keyin\[0\] " "Info: Assuming node \"keyin\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux6~455 " "Info: Detected gated clock \"Mux6~455\" as buffer" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux6~455" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux6~454 " "Info: Detected gated clock \"Mux6~454\" as buffer" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux6~454" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_TSU_RESULT" "keyvalue\[3\]\$latch keyin\[1\] keydrv\[1\] 2.770 ns register " "Info: tsu for register \"keyvalue\[3\]\$latch\" (data pin = \"keyin\[1\]\", clock pin = \"keydrv\[1\]\") is 2.770 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.057 ns + Longest pin register " "Info: + Longest pin to register delay is 9.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[1\] 1 CLK PIN_39 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_39; Fanout = 7; CLK Node = 'keyin\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[1] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.913 ns) + CELL(0.454 ns) 6.502 ns Mux4~559 2 COMB LC_X16_Y13_N2 2 " "Info: 2: + IC(4.913 ns) + CELL(0.454 ns) = 6.502 ns; Loc. = LC_X16_Y13_N2; Fanout = 2; COMB Node = 'Mux4~559'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.367 ns" { keyin[1] Mux4~559 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.454 ns) 7.292 ns Mux5~533 3 COMB LC_X16_Y13_N6 1 " "Info: 3: + IC(0.336 ns) + CELL(0.454 ns) = 7.292 ns; Loc. = LC_X16_Y13_N6; Fanout = 1; COMB Node = 'Mux5~533'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.790 ns" { Mux4~559 Mux5~533 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.454 ns) 9.057 ns keyvalue\[3\]\$latch 4 REG LC_X26_Y13_N2 1 " "Info: 4: + IC(1.311 ns) + CELL(0.454 ns) = 9.057 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'keyvalue\[3\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.765 ns" { Mux5~533 keyvalue[3]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.497 ns ( 27.57 % ) " "Info: Total cell delay = 2.497 ns ( 27.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.560 ns ( 72.43 % ) " "Info: Total interconnect delay = 6.560 ns ( 72.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.057 ns" { keyin[1] Mux4~559 Mux5~533 keyvalue[3]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.057 ns" { keyin[1] keyin[1]~out0 Mux4~559 Mux5~533 keyvalue[3]$latch } { 0.000ns 0.000ns 4.913ns 0.336ns 1.311ns } { 0.000ns 1.135ns 0.454ns 0.454ns 0.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.648 ns + " "Info: + Micro setup delay of destination is 0.648 ns" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydrv\[1\] destination 6.935 ns - Shortest register " "Info: - Shortest clock path from clock \"keydrv\[1\]\" to destination register is 6.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keydrv\[1\] 1 CLK PIN_87 8 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_87; Fanout = 8; CLK Node = 'keydrv\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keydrv[1] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.088 ns) 2.229 ns Mux6~455 2 COMB LC_X16_Y12_N0 1 " "Info: 2: + IC(1.006 ns) + CELL(0.088 ns) = 2.229 ns; Loc. = LC_X16_Y12_N0; Fanout = 1; COMB Node = 'Mux6~455'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { keydrv[1] Mux6~455 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 2.457 ns Mux6~456 3 COMB LC_X16_Y12_N1 5 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 2.457 ns; Loc. = LC_X16_Y12_N1; Fanout = 5; COMB Node = 'Mux6~456'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { Mux6~455 Mux6~456 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.390 ns) + CELL(0.088 ns) 6.935 ns keyvalue\[3\]\$latch 4 REG LC_X26_Y13_N2 1 " "Info: 4: + IC(4.390 ns) + CELL(0.088 ns) = 6.935 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'keyvalue\[3\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.478 ns" { Mux6~456 keyvalue[3]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 20.17 % ) " "Info: Total cell delay = 1.399 ns ( 20.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.536 ns ( 79.83 % ) " "Info: Total interconnect delay = 5.536 ns ( 79.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.935 ns" { keydrv[1] Mux6~455 Mux6~456 keyvalue[3]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.935 ns" { keydrv[1] keydrv[1]~out0 Mux6~455 Mux6~456 keyvalue[3]$latch } { 0.000ns 0.000ns 1.006ns 0.140ns 4.390ns } { 0.000ns 1.135ns 0.088ns 0.088ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.057 ns" { keyin[1] Mux4~559 Mux5~533 keyvalue[3]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.057 ns" { keyin[1] keyin[1]~out0 Mux4~559 Mux5~533 keyvalue[3]$latch } { 0.000ns 0.000ns 4.913ns 0.336ns 1.311ns } { 0.000ns 1.135ns 0.454ns 0.454ns 0.454ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.935 ns" { keydrv[1] Mux6~455 Mux6~456 keyvalue[3]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.935 ns" { keydrv[1] keydrv[1]~out0 Mux6~455 Mux6~456 keyvalue[3]$latch } { 0.000ns 0.000ns 1.006ns 0.140ns 4.390ns } { 0.000ns 1.135ns 0.088ns 0.088ns 0.088ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "keyin\[1\] keyvalue\[1\] keyvalue\[1\]\$latch 12.084 ns register " "Info: tco from clock \"keyin\[1\]\" to destination pin \"keyvalue\[1\]\" through register \"keyvalue\[1\]\$latch\" is 12.084 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyin\[1\] source 8.210 ns + Longest register " "Info: + Longest clock path from clock \"keyin\[1\]\" to source register is 8.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns keyin\[1\] 1 CLK PIN_39 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_39; Fanout = 7; CLK Node = 'keyin\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[1] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.340 ns) 3.126 ns Mux6~454 2 COMB LC_X16_Y12_N9 1 " "Info: 2: + IC(1.651 ns) + CELL(0.340 ns) = 3.126 ns; Loc. = LC_X16_Y12_N9; Fanout = 1; COMB Node = 'Mux6~454'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.991 ns" { keyin[1] Mux6~454 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.225 ns) 3.695 ns Mux6~456 3 COMB LC_X16_Y12_N1 5 " "Info: 3: + IC(0.344 ns) + CELL(0.225 ns) = 3.695 ns; Loc. = LC_X16_Y12_N1; Fanout = 5; COMB Node = 'Mux6~456'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { Mux6~454 Mux6~456 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.427 ns) + CELL(0.088 ns) 8.210 ns keyvalue\[1\]\$latch 4 REG LC_X16_Y12_N3 1 " "Info: 4: + IC(4.427 ns) + CELL(0.088 ns) = 8.210 ns; Loc. = LC_X16_Y12_N3; Fanout = 1; REG Node = 'keyvalue\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.515 ns" { Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.788 ns ( 21.78 % ) " "Info: Total cell delay = 1.788 ns ( 21.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.422 ns ( 78.22 % ) " "Info: Total interconnect delay = 6.422 ns ( 78.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.210 ns" { keyin[1] Mux6~454 Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.210 ns" { keyin[1] keyin[1]~out0 Mux6~454 Mux6~456 keyvalue[1]$latch } { 0.000ns 0.000ns 1.651ns 0.344ns 4.427ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.874 ns + Longest register pin " "Info: + Longest register to pin delay is 3.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyvalue\[1\]\$latch 1 REG LC_X16_Y12_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N3; Fanout = 1; REG Node = 'keyvalue\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyvalue[1]$latch } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.240 ns) + CELL(1.634 ns) 3.874 ns keyvalue\[1\] 2 PIN PIN_57 0 " "Info: 2: + IC(2.240 ns) + CELL(1.634 ns) = 3.874 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'keyvalue\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.874 ns" { keyvalue[1]$latch keyvalue[1] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/altera/70/quartus/work/键盘接口电路/keydecoder/keydecoder.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 42.18 % ) " "Info: Total cell delay = 1.634 ns ( 42.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.240 ns ( 57.82 % ) " "Info: Total interconnect delay = 2.240 ns ( 57.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.874 ns" { keyvalue[1]$latch keyvalue[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.874 ns" { keyvalue[1]$latch keyvalue[1] } { 0.000ns 2.240ns } { 0.000ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.210 ns" { keyin[1] Mux6~454 Mux6~456 keyvalue[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.210 ns" { keyin[1] keyin[1]~out0 Mux6~454 Mux6~456 keyvalue[1]$latch } { 0.000ns 0.000ns 1.651ns 0.344ns 4.427ns } { 0.000ns 1.135ns 0.340ns 0.225ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.874 ns" { keyvalue[1]$latch keyvalue[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.874 ns" { keyvalue[1]$latch keyvalue[1] } { 0.000ns 2.240ns } { 0.000ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}