keydecoder.map.rpt

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件

+---------------------------------------------+-----------+
; Total logic elements                        ; 22        ;
;     -- Combinational with no register       ; 22        ;
;     -- Register only                        ; 0         ;
;     -- Combinational with a register        ; 0         ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 11        ;
;     -- 3 input functions                    ; 7         ;
;     -- 2 input functions                    ; 3         ;
;     -- 1 input functions                    ; 0         ;
;     -- 0 input functions                    ; 1         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 22        ;
;     -- arithmetic mode                      ; 0         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 0         ;
;     -- asynchronous clear/load mode         ; 0         ;
;                                             ;           ;
; Total registers                             ; 0         ;
; I/O pins                                    ; 0         ;
; Maximum fan-out node                        ; keydrv[0] ;
; Maximum fan-out                             ; 8         ;
; Total fan-out                               ; 77        ;
; Average fan-out                             ; 2.08      ;
+---------------------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |keydecoder                ; 22 (22)     ; 0            ; 0           ; 0    ; 0            ; 22 (22)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |keydecoder         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; keyvalue[0]$latch                                  ; Mux6                ; yes                    ;
; keyvalue[1]$latch                                  ; Mux6                ; yes                    ;
; keyvalue[2]$latch                                  ; Mux6                ; yes                    ;
; keyvalue[3]$latch                                  ; Mux6                ; yes                    ;
; functionkey$latch                                  ; Mux6                ; yes                    ;
; Number of user-specified and inferred latches = 5  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; q1                                    ; Stuck at VCC due to stuck port data_in ;
; q2                                    ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 2 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Jun 26 19:41:01 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keydecoder -c keydecoder
Info: Found 2 design units, including 1 entities, in source file keydecoder.vhd
    Info: Found design unit 1: keydecoder-behav
    Info: Found entity 1: keydecoder
Info: Elaborating entity "keydecoder" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable "keyvalue", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable "temp_pressed", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at keydecoder.vhd(20): inferring latch(es) for signal or variable "functionkey", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(48): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(48): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "functionkey"
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "temp_pressed"
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "keyvalue[0]"
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "keyvalue[1]"
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "keyvalue[2]"
Info (10041): Verilog HDL or VHDL info at keydecoder.vhd(20): inferred latch for "keyvalue[3]"
Info: Power-up level of register "q1" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "q1" with stuck data_in port to stuck value VCC
Info: Power-up level of register "q2" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "q2" with stuck data_in port to stuck value VCC
Warning: Latch keyvalue[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keydrv[1]
Warning: Latch keyvalue[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keyin[0]
Warning: Latch keyvalue[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keydrv[2]
Warning: Latch keyvalue[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keydrv[0]
Warning: Latch functionkey$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keydrv[1]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "keypressed" stuck at GND
Info: Implemented 37 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 6 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
    Info: Allocated 133 megabytes of memory during processing
    Info: Processing ended: Thu Jun 26 19:41:04 2008
    Info: Elapsed time: 00:00:03