vpc.tan.rpt

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

; N/A   ; None         ; 10.354 ns  ; ad_control:inst|dataout[6] ; dataout3[1] ; inclk      ;
; N/A   ; None         ; 10.115 ns  ; ad_control:inst|dataout[7] ; dataout3[1] ; inclk      ;
; N/A   ; None         ; 8.686 ns   ; ad_control:inst|rd         ; rd          ; inclk      ;
; N/A   ; None         ; 8.686 ns   ; ad_control:inst|rd         ; cs          ; inclk      ;
+-------+--------------+------------+----------------------------+-------------+------------+


+---------------------------------------------------------------------------------------------+
; th                                                                                          ;
+---------------+-------------+-----------+-----------+----------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                         ; To Clock ;
+---------------+-------------+-----------+-----------+----------------------------+----------+
; N/A           ; None        ; 0.775 ns  ; datain[7] ; ad_control:inst|dataout[7] ; inclk    ;
; N/A           ; None        ; 0.396 ns  ; datain[2] ; ad_control:inst|dataout[2] ; inclk    ;
; N/A           ; None        ; 0.242 ns  ; busy      ; ad_control:inst|state.s1   ; inclk    ;
; N/A           ; None        ; 0.241 ns  ; busy      ; ad_control:inst|state.s3   ; inclk    ;
; N/A           ; None        ; 0.157 ns  ; datain[1] ; ad_control:inst|dataout[1] ; inclk    ;
; N/A           ; None        ; 0.150 ns  ; datain[4] ; ad_control:inst|dataout[4] ; inclk    ;
; N/A           ; None        ; 0.093 ns  ; datain[5] ; ad_control:inst|dataout[5] ; inclk    ;
; N/A           ; None        ; 0.092 ns  ; datain[6] ; ad_control:inst|dataout[6] ; inclk    ;
; N/A           ; None        ; -0.165 ns ; datain[0] ; ad_control:inst|dataout[0] ; inclk    ;
; N/A           ; None        ; -0.281 ns ; datain[3] ; ad_control:inst|dataout[3] ; inclk    ;
+---------------+-------------+-----------+-----------+----------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 25 21:40:23 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vpc -c vpc --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "inclk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "division:inst2|outclk" as buffer
Info: Clock "inclk" has Internal fmax of 331.56 MHz between source register "division:inst2|count[5]" and destination register "division:inst2|count[6]" (period= 3.016 ns)
    Info: + Longest register to register delay is 2.814 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'division:inst2|count[5]'
        Info: 2: + IC(0.882 ns) + CELL(0.443 ns) = 1.325 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; COMB Node = 'division:inst2|Add0~122COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.468 ns) = 1.793 ns; Loc. = LC_X9_Y6_N6; Fanout = 1; COMB Node = 'division:inst2|Add0~119'
        Info: 4: + IC(0.932 ns) + CELL(0.089 ns) = 2.814 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'division:inst2|count[6]'
        Info: Total cell delay = 1.000 ns ( 35.54 % )
        Info: Total interconnect delay = 1.814 ns ( 64.46 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "inclk" to destination register is 2.107 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'
            Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'division:inst2|count[6]'
            Info: Total cell delay = 1.677 ns ( 79.59 % )
            Info: Total interconnect delay = 0.430 ns ( 20.41 % )
        Info: - Longest clock path from clock "inclk" to source register is 2.107 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'
            Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'division:inst2|count[5]'
            Info: Total cell delay = 1.677 ns ( 79.59 % )
            Info: Total interconnect delay = 0.430 ns ( 20.41 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "ad_control:inst|dataout[3]" (data pin = "datain[3]", clock pin = "inclk") is 0.322 ns
    Info: + Longest pin to register delay is 5.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'datain[3]'
        Info: 2: + IC(4.585 ns) + CELL(0.089 ns) = 5.809 ns; Loc. = LC_X26_Y9_N4; Fanout = 19; REG Node = 'ad_control:inst|dataout[3]'
        Info: Total cell delay = 1.224 ns ( 21.07 % )
        Info: Total interconnect delay = 4.585 ns ( 78.93 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "inclk" to destination register is 5.516 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'
        Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N4; Fanout = 14; REG Node = 'division:inst2|outclk'
        Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X26_Y9_N4; Fanout = 19; REG Node = 'ad_control:inst|dataout[3]'
        Info: Total cell delay = 2.397 ns ( 43.46 % )
        Info: Total interconnect delay = 3.119 ns ( 56.54 % )
Info: tco from clock "inclk" to destination pin "dataout1[3]" through register "ad_control:inst|dataout[4]" is 23.417 ns
    Info: + Longest clock path from clock "inclk" to source register is 5.516 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'
        Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N4; Fanout = 14; REG Node = 'division:inst2|outclk'
        Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X25_Y9_N5; Fanout = 19; REG Node = 'ad_control:inst|dataout[4]'
        Info: Total cell delay = 2.397 ns ( 43.46 % )
        Info: Total interconnect delay = 3.119 ns ( 56.54 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 17.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y9_N5; Fanout = 19; REG Node = 'ad_control:inst|dataout[4]'
        Info: 2: + IC(0.926 ns) + CELL(0.088 ns) = 1.014 ns; Loc. = LC_X26_Y9_N4; Fanout = 2; COMB Node = 'code:inst1|LessThan7~110'
        Info: 3: + IC(0.834 ns) + CELL(0.454 ns) = 2.302 ns; Loc. = LC_X26_Y9_N5; Fanout = 2; COMB Node = 'code:inst1|process0~1540'
        Info: 4: + IC(0.528 ns) + CELL(0.340 ns) = 3.170 ns; Loc. = LC_X25_Y9_N7; Fanout = 11; COMB Node = 'code:inst1|process0~1541'
        Info: 5: + IC(1.233 ns) + CELL(0.340 ns) = 4.743 ns; Loc. = LC_X23_Y8_N5; Fanout = 1; COMB Node = 'code:inst1|Selector3~230'
        Info: 6: + IC(0.850 ns) + CELL(0.454 ns) = 6.047 ns; Loc. = LC_X25_Y8_N5; Fanout = 17; COMB Node = 'code:inst1|Selector3~231'
        Info: 7: + IC(1.591 ns) + CELL(0.340 ns) = 7.978 ns; Loc. = LC_X23_Y7_N5; Fanout = 2; COMB Node = 'code:inst1|process0~1555'
        Info: 8: + IC(0.322 ns) + CELL(0.340 ns) = 8.640 ns; Loc. = LC_X23_Y7_N4; Fanout = 3; COMB Node = 'code:inst1|process0~1563'
        Info: 9: + IC(0.969 ns) + CELL(0.088 ns) = 9.697 ns; Loc. = LC_X22_Y6_N0; Fanout = 2; COMB Node = 'code:inst1|WideOr4~17'
        Info: 10: + IC(0.917 ns) + CELL(0.340 ns) = 10.954 ns; Loc. = LC_X22_Y7_N5; Fanout = 1; COMB Node = 'code:inst1|Selector6~277'
        Info: 11: + IC(0.312 ns) + CELL(0.340 ns) = 11.606 ns; Loc. = LC_X22_Y7_N4; Fanout = 4; COMB Node = 'code:inst1|Selector6~279'
        Info: 12: + IC(0.989 ns) + CELL(0.088 ns) = 12.683 ns; Loc. = LC_X22_Y6_N6; Fanout = 3; COMB Node = 'code:inst1|Mux2~29'
        Info: 13: + IC(3.411 ns) + CELL(1.634 ns) = 17.728 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'dataout1[3]'
        Info: Total cell delay = 4.846 ns ( 27.34 % )
        Info: Total interconnect delay = 12.882 ns ( 72.66 % )
Info: th for register "ad_control:inst|dataout[7]" (data pin = "datain[7]", clock pin = "inclk") is 0.775 ns
    Info: + Longest clock path from clock "inclk" to destination register is 5.516 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'
        Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N4; Fanout = 14; REG Node = 'division:inst2|outclk'
        Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X26_Y9_N1; Fanout = 8; REG Node = 'ad_control:inst|dataout[7]'
        Info: Total cell delay = 2.397 ns ( 43.46 % )
        Info: Total interconnect delay = 3.119 ns ( 56.54 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 4.753 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_69; Fanout = 1; PIN Node = 'datain[7]'
        Info: 2: + IC(3.534 ns) + CELL(0.089 ns) = 4.753 ns; Loc. = LC_X26_Y9_N1; Fanout = 8; REG Node = 'ad_control:inst|dataout[7]'
        Info: Total cell delay = 1.219 ns ( 25.65 % )
        Info: Total interconnect delay = 3.534 ns ( 74.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Wed Jun 25 21:40:25 2008
    Info: Elapsed time: 00:00:02