ad_control.tan.rpt

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

; N/A   ; None         ; 3.514 ns   ; datain[3] ; dataout[3]~reg0 ; clk      ;
; N/A   ; None         ; 3.386 ns   ; datain[6] ; dataout[6]~reg0 ; clk      ;
; N/A   ; None         ; 3.269 ns   ; datain[0] ; dataout[0]~reg0 ; clk      ;
; N/A   ; None         ; 3.162 ns   ; datain[2] ; dataout[2]~reg0 ; clk      ;
; N/A   ; None         ; 3.157 ns   ; datain[5] ; dataout[5]~reg0 ; clk      ;
; N/A   ; None         ; 2.640 ns   ; datain[4] ; dataout[4]~reg0 ; clk      ;
; N/A   ; None         ; 0.029 ns   ; datain[7] ; dataout[7]~reg0 ; clk      ;
+-------+--------------+------------+-----------+-----------------+----------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To         ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A   ; None         ; 5.643 ns   ; rd~reg0         ; rd         ; clk        ;
; N/A   ; None         ; 5.643 ns   ; rd~reg0         ; cs         ; clk        ;
; N/A   ; None         ; 5.547 ns   ; dataout[2]~reg0 ; dataout[2] ; clk        ;
; N/A   ; None         ; 5.543 ns   ; dataout[0]~reg0 ; dataout[0] ; clk        ;
; N/A   ; None         ; 5.161 ns   ; dataout[3]~reg0 ; dataout[3] ; clk        ;
; N/A   ; None         ; 5.158 ns   ; dataout[4]~reg0 ; dataout[4] ; clk        ;
; N/A   ; None         ; 5.157 ns   ; dataout[1]~reg0 ; dataout[1] ; clk        ;
; N/A   ; None         ; 5.053 ns   ; dataout[7]~reg0 ; dataout[7] ; clk        ;
; N/A   ; None         ; 5.045 ns   ; dataout[6]~reg0 ; dataout[6] ; clk        ;
; N/A   ; None         ; 4.820 ns   ; dataout[5]~reg0 ; dataout[5] ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+-----------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To              ; To Clock ;
+---------------+-------------+-----------+-----------+-----------------+----------+
; N/A           ; None        ; 0.012 ns  ; datain[7] ; dataout[7]~reg0 ; clk      ;
; N/A           ; None        ; -2.599 ns ; datain[4] ; dataout[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.116 ns ; datain[5] ; dataout[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.121 ns ; datain[2] ; dataout[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.228 ns ; datain[0] ; dataout[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.345 ns ; datain[6] ; dataout[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.473 ns ; datain[3] ; dataout[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.507 ns ; busy      ; state.s3        ; clk      ;
; N/A           ; None        ; -3.730 ns ; busy      ; state.s1        ; clk      ;
; N/A           ; None        ; -3.856 ns ; datain[1] ; dataout[1]~reg0 ; clk      ;
+---------------+-------------+-----------+-----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 25 20:43:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ad_control -c ad_control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "state.s1" and destination register "dataout[0]~reg0"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.108 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N4; Fanout = 10; REG Node = 'state.s1'
            Info: 2: + IC(0.441 ns) + CELL(0.667 ns) = 1.108 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'dataout[0]~reg0'
            Info: Total cell delay = 0.667 ns ( 60.20 % )
            Info: Total interconnect delay = 0.441 ns ( 39.80 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.139 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'dataout[0]~reg0'
                Info: Total cell delay = 1.677 ns ( 78.40 % )
                Info: Total interconnect delay = 0.462 ns ( 21.60 % )
            Info: - Longest clock path from clock "clk" to source register is 2.139 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N4; Fanout = 10; REG Node = 'state.s1'
                Info: Total cell delay = 1.677 ns ( 78.40 % )
                Info: Total interconnect delay = 0.462 ns ( 21.60 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "dataout[1]~reg0" (data pin = "datain[1]", clock pin = "clk") is 3.897 ns
    Info: + Longest pin to register delay is 6.007 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_48; Fanout = 1; PIN Node = 'datain[1]'
        Info: 2: + IC(4.783 ns) + CELL(0.089 ns) = 6.007 ns; Loc. = LC_X26_Y10_N6; Fanout = 1; REG Node = 'dataout[1]~reg0'
        Info: Total cell delay = 1.224 ns ( 20.38 % )
        Info: Total interconnect delay = 4.783 ns ( 79.62 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N6; Fanout = 1; REG Node = 'dataout[1]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
Info: tco from clock "clk" to destination pin "rd" through register "rd~reg0" is 5.643 ns
    Info: + Longest clock path from clock "clk" to source register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N5; Fanout = 3; REG Node = 'rd~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.331 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N5; Fanout = 3; REG Node = 'rd~reg0'
        Info: 2: + IC(1.709 ns) + CELL(1.622 ns) = 3.331 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'rd'
        Info: Total cell delay = 1.622 ns ( 48.69 % )
        Info: Total interconnect delay = 1.709 ns ( 51.31 % )
Info: th for register "dataout[7]~reg0" (data pin = "datain[7]", clock pin = "clk") is 0.012 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N8; Fanout = 1; REG Node = 'dataout[7]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 1; PIN Node = 'datain[7]'
        Info: 2: + IC(0.771 ns) + CELL(0.238 ns) = 2.139 ns; Loc. = LC_X26_Y10_N8; Fanout = 1; REG Node = 'dataout[7]~reg0'
        Info: Total cell delay = 1.368 ns ( 63.96 % )
        Info: Total interconnect delay = 0.771 ns ( 36.04 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Wed Jun 25 20:43:13 2008
    Info: Elapsed time: 00:00:01