📄 vpc.sim.rpt
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; |vpc|code:inst1|Selector2~353 ; |vpc|code:inst1|Selector2~353 ; combout ;
; |vpc|code:inst1|Add3~183 ; |vpc|code:inst1|Add3~183 ; combout ;
; |vpc|code:inst1|process0~1548 ; |vpc|code:inst1|process0~1548 ; combout ;
; |vpc|code:inst1|Selector2~355 ; |vpc|code:inst1|Selector2~355 ; combout ;
; |vpc|code:inst1|Selector1~292 ; |vpc|code:inst1|Selector1~292 ; combout ;
; |vpc|code:inst1|Selector1~293 ; |vpc|code:inst1|Selector1~293 ; combout ;
; |vpc|code:inst1|Add1~130 ; |vpc|code:inst1|Add1~130 ; combout ;
; |vpc|code:inst1|Selector1~294 ; |vpc|code:inst1|Selector1~294 ; combout ;
; |vpc|code:inst1|Selector4~219 ; |vpc|code:inst1|Selector4~219 ; combout ;
; |vpc|code:inst1|Selector4~221 ; |vpc|code:inst1|Selector4~221 ; combout ;
; |vpc|code:inst1|Selector3~229 ; |vpc|code:inst1|Selector3~229 ; combout ;
; |vpc|code:inst1|Selector3~231 ; |vpc|code:inst1|Selector3~231 ; combout ;
; |vpc|ad_control:inst|dataout[0] ; |vpc|code:inst1|process0~1549 ; combout ;
; |vpc|code:inst1|process0~1551 ; |vpc|code:inst1|process0~1551 ; combout ;
; |vpc|code:inst1|Selector4~222 ; |vpc|code:inst1|Selector4~222 ; combout ;
; |vpc|code:inst1|process0~1552 ; |vpc|code:inst1|process0~1552 ; combout ;
; |vpc|code:inst1|LessThan15~89 ; |vpc|code:inst1|LessThan15~89 ; combout ;
; |vpc|code:inst1|process0~1555 ; |vpc|code:inst1|process0~1555 ; combout ;
; |vpc|code:inst1|process0~1556 ; |vpc|code:inst1|process0~1556 ; combout ;
; |vpc|code:inst1|process0~1557 ; |vpc|code:inst1|process0~1557 ; combout ;
; |vpc|code:inst1|WideOr6~9 ; |vpc|code:inst1|WideOr6~9 ; combout ;
; |vpc|code:inst1|process0~1558 ; |vpc|code:inst1|process0~1558 ; combout ;
; |vpc|code:inst1|process0~1559 ; |vpc|code:inst1|process0~1559 ; combout ;
; |vpc|code:inst1|Add6~41 ; |vpc|code:inst1|Add6~41 ; combout ;
; |vpc|code:inst1|process0~1560 ; |vpc|code:inst1|process0~1560 ; combout ;
; |vpc|code:inst1|process0~1561 ; |vpc|code:inst1|process0~1561 ; combout ;
; |vpc|code:inst1|Mux0~169 ; |vpc|code:inst1|Mux0~169 ; combout ;
; |vpc|code:inst1|process0~1562 ; |vpc|code:inst1|process0~1562 ; combout ;
; |vpc|code:inst1|Mux0~170 ; |vpc|code:inst1|Mux0~170 ; combout ;
; |vpc|code:inst1|Mux0~171 ; |vpc|code:inst1|Mux0~171 ; combout ;
; |vpc|code:inst1|LessThan19~74 ; |vpc|code:inst1|LessThan19~74 ; combout ;
; |vpc|code:inst1|process0~1564 ; |vpc|code:inst1|process0~1564 ; combout ;
; |vpc|code:inst1|Selector5~84 ; |vpc|code:inst1|Selector5~84 ; combout ;
; |vpc|code:inst1|process0~1565 ; |vpc|code:inst1|process0~1565 ; combout ;
; |vpc|code:inst1|Mux0~173 ; |vpc|code:inst1|Mux0~173 ; combout ;
; |vpc|code:inst1|WideOr4~17 ; |vpc|code:inst1|WideOr4~17 ; combout ;
; |vpc|code:inst1|Selector6~277 ; |vpc|code:inst1|Selector6~277 ; combout ;
; |vpc|code:inst1|process0~1566 ; |vpc|code:inst1|process0~1566 ; combout ;
; |vpc|code:inst1|Selector6~278 ; |vpc|code:inst1|Selector6~278 ; combout ;
; |vpc|code:inst1|Selector6~279 ; |vpc|code:inst1|Selector6~279 ; combout ;
; |vpc|code:inst1|Mux0~174 ; |vpc|code:inst1|Mux0~174 ; combout ;
; |vpc|code:inst1|Mux1~24 ; |vpc|code:inst1|Mux1~24 ; combout ;
; |vpc|code:inst1|Mux2~29 ; |vpc|code:inst1|Mux2~29 ; combout ;
; |vpc|code:inst1|Mux5~19 ; |vpc|code:inst1|Mux5~19 ; combout ;
; |vpc|code:inst1|WideOr4 ; |vpc|code:inst1|WideOr4 ; combout ;
; |vpc|code:inst1|WideOr3 ; |vpc|code:inst1|WideOr3 ; combout ;
; |vpc|code:inst1|WideOr2~27 ; |vpc|code:inst1|WideOr2~27 ; combout ;
; |vpc|code:inst1|Mux7~31 ; |vpc|code:inst1|Mux7~31 ; combout ;
; |vpc|code:inst1|Mux8~29 ; |vpc|code:inst1|Mux8~29 ; combout ;
; |vpc|code:inst1|Mux9~15 ; |vpc|code:inst1|Mux9~15 ; combout ;
; |vpc|code:inst1|Mux10~31 ; |vpc|code:inst1|Mux10~31 ; combout ;
; |vpc|code:inst1|Mux11~33 ; |vpc|code:inst1|Mux11~33 ; combout ;
; |vpc|code:inst1|Mux12~32 ; |vpc|code:inst1|Mux12~32 ; combout ;
; |vpc|code:inst1|Mux13~33 ; |vpc|code:inst1|Mux13~33 ; combout ;
; |vpc|code:inst1|Mux14~25 ; |vpc|code:inst1|Mux14~25 ; combout ;
; |vpc|code:inst1|process0~1567 ; |vpc|code:inst1|process0~1567 ; combout ;
; |vpc|code:inst1|Mux15~107 ; |vpc|code:inst1|Mux15~107 ; combout ;
; |vpc|code:inst1|Mux17~144 ; |vpc|code:inst1|Mux17~144 ; combout ;
; |vpc|code:inst1|Mux18~45 ; |vpc|code:inst1|Mux18~45 ; combout ;
; |vpc|ad_control:inst|state.s1 ; |vpc|ad_control:inst|state.s1 ; regout ;
; |vpc|ad_control:inst|state.s2 ; |vpc|ad_control:inst|state.s2 ; regout ;
; |vpc|division:inst2|outclk ; |vpc|division:inst2|outclk ; regout ;
; |vpc|ad_control:inst|state.s4 ; |vpc|ad_control:inst|state.s4 ; regout ;
; |vpc|division:inst2|count[1] ; |vpc|division:inst2|count[1] ; regout ;
; |vpc|division:inst2|count[0] ; |vpc|division:inst2|count[0] ; regout ;
; |vpc|division:inst2|LessThan0~95 ; |vpc|division:inst2|LessThan0~95 ; combout ;
; |vpc|division:inst2|count[3] ; |vpc|division:inst2|count[3] ; regout ;
; |vpc|ad_control:inst|state.s3 ; |vpc|ad_control:inst|state.s3 ; regout ;
; |vpc|division:inst2|count[2] ; |vpc|division:inst2|Equal0~70 ; combout ;
; |vpc|division:inst2|count[2] ; |vpc|division:inst2|count[2] ; regout ;
; |vpc|code:inst1|Add3~184 ; |vpc|code:inst1|Add3~184 ; combout ;
; |vpc|code:inst1|LessThan15~90 ; |vpc|code:inst1|LessThan15~90 ; combout ;
; |vpc|code:inst1|Selector7~61 ; |vpc|code:inst1|Selector7~61 ; combout ;
; |vpc|cs ; |vpc|cs ; padio ;
; |vpc|rd ; |vpc|rd ; padio ;
; |vpc|dataout1[6] ; |vpc|dataout1[6] ; padio ;
; |vpc|dataout1[5] ; |vpc|dataout1[5] ; padio ;
; |vpc|dataout1[4] ; |vpc|dataout1[4] ; padio ;
; |vpc|dataout1[3] ; |vpc|dataout1[3] ; padio ;
; |vpc|dataout1[2] ; |vpc|dataout1[2] ; padio ;
; |vpc|dataout1[1] ; |vpc|dataout1[1] ; padio ;
; |vpc|dataout1[0] ; |vpc|dataout1[0] ; padio ;
; |vpc|dataout2[6] ; |vpc|dataout2[6] ; padio ;
; |vpc|dataout2[5] ; |vpc|dataout2[5] ; padio ;
; |vpc|dataout2[4] ; |vpc|dataout2[4] ; padio ;
; |vpc|dataout2[3] ; |vpc|dataout2[3] ; padio ;
; |vpc|dataout2[2] ; |vpc|dataout2[2] ; padio ;
; |vpc|dataout2[1] ; |vpc|dataout2[1] ; padio ;
; |vpc|dataout2[0] ; |vpc|dataout2[0] ; padio ;
; |vpc|dataout3[6] ; |vpc|dataout3[6] ; padio ;
; |vpc|dataout3[5] ; |vpc|dataout3[5] ; padio ;
; |vpc|dataout3[3] ; |vpc|dataout3[3] ; padio ;
; |vpc|dataout3[2] ; |vpc|dataout3[2] ; padio ;
; |vpc|dataout3[0] ; |vpc|dataout3[0] ; padio ;
; |vpc|inclk ; |vpc|inclk ; combout ;
+----------------------------------+-----------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------+-----------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------+-----------------------------------+------------------+
; |vpc|code:inst1|Add2~261 ; |vpc|code:inst1|Add2~262 ; cout0 ;
; |vpc|code:inst1|Add2~261 ; |vpc|code:inst1|Add2~262COUT1 ; cout1 ;
; |vpc|code:inst1|Add0~183 ; |vpc|code:inst1|Add0~184 ; cout0 ;
; |vpc|code:inst1|Add0~183 ; |vpc|code:inst1|Add0~184COUT1 ; cout1 ;
; |vpc|code:inst1|Add4~291 ; |vpc|code:inst1|Add4~292 ; cout0 ;
; |vpc|code:inst1|Add4~291 ; |vpc|code:inst1|Add4~292COUT1 ; cout1 ;
; |vpc|code:inst1|Add4~293 ; |vpc|code:inst1|Add4~293 ; combout ;
; |vpc|code:inst1|Add0~185 ; |vpc|code:inst1|Add0~185 ; combout ;
; |vpc|code:inst1|Add2~263 ; |vpc|code:inst1|Add2~263 ; combout ;
; |vpc|code:inst1|Add0~187 ; |vpc|code:inst1|Add0~188 ; cout0 ;
; |vpc|code:inst1|Add0~187 ; |vpc|code:inst1|Add0~188COUT1 ; cout1 ;
; |vpc|code:inst1|Add2~265 ; |vpc|code:inst1|Add2~266 ; cout0 ;
; |vpc|code:inst1|Add2~265 ; |vpc|code:inst1|Add2~266COUT1 ; cout1 ;
; |vpc|code:inst1|Add4~295 ; |vpc|code:inst1|Add4~296 ; cout0 ;
; |vpc|code:inst1|Add4~295 ; |vpc|code:inst1|Add4~296COUT1 ; cout1 ;
; |vpc|division:inst2|Add0~117 ; |vpc|division:inst2|Add0~117 ; combout ;
; |vpc|division:inst2|Add0~119 ; |vpc|division:inst2|Add0~119 ; combout ;
; |vpc|division:inst2|Add0~119 ; |vpc|division:inst2|Add0~120 ; cout0 ;
; |vpc|division:inst2|Add0~119 ; |vpc|division:inst2|Add0~120COUT1 ; cout1 ;
; |vpc|division:inst2|Add0~121 ; |vpc|division:inst2|Add0~121 ; combout ;
; |vpc|division:inst2|Add0~121 ; |vpc|division:inst2|Add0~122 ; cout0 ;
; |vpc|division:inst2|Add0~121 ; |vpc|division:inst2|Add0~122COUT1 ; cout1 ;
; |vpc|division:inst2|Add0~123 ; |vpc|division:inst2|Add0~124 ; cout ;
; |vpc|code:inst1|process0~1541 ; |vpc|code:inst1|process0~1541 ; combout ;
; |vpc|code:inst1|LessThan11~117 ; |vpc|code:inst1|LessThan11~117 ; combout ;
; |vpc|code:inst1|process0~1542 ; |vpc|code:inst1|process0~1542 ; combout ;
; |vpc|code:inst1|process0~1543 ; |vpc|code:inst1|process0~1543 ; combout ;
; |vpc|ad_control:inst|dataout[7] ; |vpc|code:inst1|process0~1545 ; combout ;
; |vpc|code:inst1|Selector0~344 ; |vpc|code:inst1|Selector0~344 ; combout ;
; |vpc|code:inst1|Selector2~354 ; |vpc|code:inst1|Selector2~354 ; combout ;
; |vpc|code:inst1|Selector4~220 ; |vpc|code:inst1|Selector4~220 ; combout ;
; |vpc|code:inst1|Selector3~230 ; |vpc|code:inst1|Selector3~230 ; combout ;
; |vpc|code:inst1|process0~1550 ; |vpc|code:inst1|process0~1550 ; combout ;
; |vpc|code:inst1|Add2~267 ; |vpc|code:inst1|Add2~267 ; combout ;
; |vpc|code:inst1|process0~1553 ; |vpc|code:inst1|process0~1553 ; combout ;
; |vpc|code:inst1|WideOr3~5 ; |vpc|code:inst1|WideOr3~5 ; combout ;
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