vpc.tan.qmsg

来自「电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "division:inst2\|outclk " "Info: Detected ripple clock \"division:inst2\|outclk\" as buffer" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 7 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "division:inst2\|outclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "inclk register division:inst2\|count\[5\] register division:inst2\|count\[6\] 331.56 MHz 3.016 ns Internal " "Info: Clock \"inclk\" has Internal fmax of 331.56 MHz between source register \"division:inst2\|count\[5\]\" and destination register \"division:inst2\|count\[6\]\" (period= 3.016 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.814 ns + Longest register register " "Info: + Longest register to register delay is 2.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns division:inst2\|count\[5\] 1 REG LC_X11_Y6_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'division:inst2\|count\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { division:inst2|count[5] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.882 ns) + CELL(0.443 ns) 1.325 ns division:inst2\|Add0~122COUT1 2 COMB LC_X9_Y6_N5 2 " "Info: 2: + IC(0.882 ns) + CELL(0.443 ns) = 1.325 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; COMB Node = 'division:inst2\|Add0~122COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { division:inst2|count[5] division:inst2|Add0~122COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.793 ns division:inst2\|Add0~119 3 COMB LC_X9_Y6_N6 1 " "Info: 3: + IC(0.000 ns) + CELL(0.468 ns) = 1.793 ns; Loc. = LC_X9_Y6_N6; Fanout = 1; COMB Node = 'division:inst2\|Add0~119'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { division:inst2|Add0~122COUT1 division:inst2|Add0~119 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.089 ns) 2.814 ns division:inst2\|count\[6\] 4 REG LC_X9_Y7_N2 4 " "Info: 4: + IC(0.932 ns) + CELL(0.089 ns) = 2.814 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'division:inst2\|count\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.021 ns" { division:inst2|Add0~119 division:inst2|count[6] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 35.54 % ) " "Info: Total cell delay = 1.000 ns ( 35.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.814 ns ( 64.46 % ) " "Info: Total interconnect delay = 1.814 ns ( 64.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.814 ns" { division:inst2|count[5] division:inst2|Add0~122COUT1 division:inst2|Add0~119 division:inst2|count[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.814 ns" { division:inst2|count[5] division:inst2|Add0~122COUT1 division:inst2|Add0~119 division:inst2|count[6] } { 0.000ns 0.882ns 0.000ns 0.932ns } { 0.000ns 0.443ns 0.468ns 0.089ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.107 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns inclk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 120 -40 128 136 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns division:inst2\|count\[6\] 2 REG LC_X9_Y7_N2 4 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'division:inst2\|count\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { inclk division:inst2|count[6] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[6] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.107 ns - Longest register " "Info: - Longest clock path from clock \"inclk\" to source register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns inclk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 120 -40 128 136 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns division:inst2\|count\[5\] 2 REG LC_X11_Y6_N2 4 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X11_Y6_N2; Fanout = 4; REG Node = 'division:inst2\|count\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { inclk division:inst2|count[5] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[5] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[6] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[5] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.814 ns" { division:inst2|count[5] division:inst2|Add0~122COUT1 division:inst2|Add0~119 division:inst2|count[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.814 ns" { division:inst2|count[5] division:inst2|Add0~122COUT1 division:inst2|Add0~119 division:inst2|count[6] } { 0.000ns 0.882ns 0.000ns 0.932ns } { 0.000ns 0.443ns 0.468ns 0.089ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[6] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { inclk division:inst2|count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { inclk inclk~out0 division:inst2|count[5] } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ad_control:inst\|dataout\[3\] datain\[3\] inclk 0.322 ns register " "Info: tsu for register \"ad_control:inst\|dataout\[3\]\" (data pin = \"datain\[3\]\", clock pin = \"inclk\") is 0.322 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.809 ns + Longest pin register " "Info: + Longest pin to register delay is 5.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns datain\[3\] 1 PIN PIN_50 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'datain\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[3] } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 312 0 168 328 "datain\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.585 ns) + CELL(0.089 ns) 5.809 ns ad_control:inst\|dataout\[3\] 2 REG LC_X26_Y9_N4 19 " "Info: 2: + IC(4.585 ns) + CELL(0.089 ns) = 5.809 ns; Loc. = LC_X26_Y9_N4; Fanout = 19; REG Node = 'ad_control:inst\|dataout\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.674 ns" { datain[3] ad_control:inst|dataout[3] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 21.07 % ) " "Info: Total cell delay = 1.224 ns ( 21.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.585 ns ( 78.93 % ) " "Info: Total interconnect delay = 4.585 ns ( 78.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.809 ns" { datain[3] ad_control:inst|dataout[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.809 ns" { datain[3] datain[3]~out0 ad_control:inst|dataout[3] } { 0.000ns 0.000ns 4.585ns } { 0.000ns 1.135ns 0.089ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 5.516 ns - Shortest register " "Info: - Shortest clock path from clock \"inclk\" to destination register is 5.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns inclk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 120 -40 128 136 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns division:inst2\|outclk 2 REG LC_X8_Y6_N4 14 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N4; Fanout = 14; REG Node = 'division:inst2\|outclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { inclk division:inst2|outclk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.547 ns) 5.516 ns ad_control:inst\|dataout\[3\] 3 REG LC_X26_Y9_N4 19 " "Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X26_Y9_N4; Fanout = 19; REG Node = 'ad_control:inst\|dataout\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.236 ns" { division:inst2|outclk ad_control:inst|dataout[3] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 43.46 % ) " "Info: Total cell delay = 2.397 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 56.54 % ) " "Info: Total interconnect delay = 3.119 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { inclk division:inst2|outclk ad_control:inst|dataout[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { inclk inclk~out0 division:inst2|outclk ad_control:inst|dataout[3] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.809 ns" { datain[3] ad_control:inst|dataout[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.809 ns" { datain[3] datain[3]~out0 ad_control:inst|dataout[3] } { 0.000ns 0.000ns 4.585ns } { 0.000ns 1.135ns 0.089ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { inclk division:inst2|outclk ad_control:inst|dataout[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { inclk inclk~out0 division:inst2|outclk ad_control:inst|dataout[3] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk dataout1\[3\] ad_control:inst\|dataout\[4\] 23.417 ns register " "Info: tco from clock \"inclk\" to destination pin \"dataout1\[3\]\" through register \"ad_control:inst\|dataout\[4\]\" is 23.417 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 5.516 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to source register is 5.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns inclk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'inclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 120 -40 128 136 "inclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.720 ns) 2.280 ns division:inst2\|outclk 2 REG LC_X8_Y6_N4 14 " "Info: 2: + IC(0.430 ns) + CELL(0.720 ns) = 2.280 ns; Loc. = LC_X8_Y6_N4; Fanout = 14; REG Node = 'division:inst2\|outclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { inclk division:inst2|outclk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.689 ns) + CELL(0.547 ns) 5.516 ns ad_control:inst\|dataout\[4\] 3 REG LC_X25_Y9_N5 19 " "Info: 3: + IC(2.689 ns) + CELL(0.547 ns) = 5.516 ns; Loc. = LC_X25_Y9_N5; Fanout = 19; REG Node = 'ad_control:inst\|dataout\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.236 ns" { division:inst2|outclk ad_control:inst|dataout[4] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 43.46 % ) " "Info: Total cell delay = 2.397 ns ( 43.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 56.54 % ) " "Info: Total interconnect delay = 3.119 ns ( 56.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { inclk division:inst2|outclk ad_control:inst|dataout[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { inclk inclk~out0 division:inst2|outclk ad_control:inst|dataout[4] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.728 ns + Longest register pin " "Info: + Longest register to pin delay is 17.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ad_control:inst\|dataout\[4\] 1 REG LC_X25_Y9_N5 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y9_N5; Fanout = 19; REG Node = 'ad_control:inst\|dataout\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad_control:inst|dataout[4] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.088 ns) 1.014 ns code:inst1\|LessThan7~110 2 COMB LC_X26_Y9_N4 2 " "Info: 2: + IC(0.926 ns) + CELL(0.088 ns) = 1.014 ns; Loc. = LC_X26_Y9_N4; Fanout = 2; COMB Node = 'code:inst1\|LessThan7~110'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.014 ns" { ad_control:inst|dataout[4] code:inst1|LessThan7~110 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.454 ns) 2.302 ns code:inst1\|process0~1540 3 COMB LC_X26_Y9_N5 2 " "Info: 3: + IC(0.834 ns) + CELL(0.454 ns) = 2.302 ns; Loc. = LC_X26_Y9_N5; Fanout = 2; COMB Node = 'code:inst1\|process0~1540'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { code:inst1|LessThan7~110 code:inst1|process0~1540 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.340 ns) 3.170 ns code:inst1\|process0~1541 4 COMB LC_X25_Y9_N7 11 " "Info: 4: + IC(0.528 ns) + CELL(0.340 ns) = 3.170 ns; Loc. = LC_X25_Y9_N7; Fanout = 11; COMB Node = 'code:inst1\|process0~1541'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.868 ns" { code:inst1|process0~1540 code:inst1|process0~1541 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.340 ns) 4.743 ns code:inst1\|Selector3~230 5 COMB LC_X23_Y8_N5 1 " "Info: 5: + IC(1.233 ns) + CELL(0.340 ns) = 4.743 ns; Loc. = LC_X23_Y8_N5; Fanout = 1; COMB Node = 'code:inst1\|Selector3~230'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { code:inst1|process0~1541 code:inst1|Selector3~230 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.850 ns) + CELL(0.454 ns) 6.047 ns code:inst1\|Selector3~231 6 COMB LC_X25_Y8_N5 17 " "Info: 6: + IC(0.850 ns) + CELL(0.454 ns) = 6.047 ns; Loc. = LC_X25_Y8_N5; Fanout = 17; COMB Node = 'code:inst1\|Selector3~231'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { code:inst1|Selector3~230 code:inst1|Selector3~231 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.340 ns) 7.978 ns code:inst1\|process0~1555 7 COMB LC_X23_Y7_N5 2 " "Info: 7: + IC(1.591 ns) + CELL(0.340 ns) = 7.978 ns; Loc. = LC_X23_Y7_N5; Fanout = 2; COMB Node = 'code:inst1\|process0~1555'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.931 ns" { code:inst1|Selector3~231 code:inst1|process0~1555 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.340 ns) 8.640 ns code:inst1\|process0~1563 8 COMB LC_X23_Y7_N4 3 " "Info: 8: + IC(0.322 ns) + CELL(0.340 ns) = 8.640 ns; Loc. = LC_X23_Y7_N4; Fanout = 3; COMB Node = 'code:inst1\|process0~1563'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.662 ns" { code:inst1|process0~1555 code:inst1|process0~1563 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.969 ns) + CELL(0.088 ns) 9.697 ns code:inst1\|WideOr4~17 9 COMB LC_X22_Y6_N0 2 " "Info: 9: + IC(0.969 ns) + CELL(0.088 ns) = 9.697 ns; Loc. = LC_X22_Y6_N0; Fanout = 2; COMB Node = 'code:inst1\|WideOr4~17'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.057 ns" { code:inst1|process0~1563 code:inst1|WideOr4~17 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.340 ns) 10.954 ns code:inst1\|Selector6~277 10 COMB LC_X22_Y7_N5 1 " "Info: 10: + IC(0.917 ns) + CELL(0.340 ns) = 10.954 ns; Loc. = LC_X22_Y7_N5; Fanout = 1; COMB Node = 'code:inst1\|Selector6~277'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { code:inst1|WideOr4~17 code:inst1|Selector6~277 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.312 ns) + CELL(0.340 ns) 11.606 ns code:inst1\|Selector6~279 11 COMB LC_X22_Y7_N4 4 " "Info: 11: + IC(0.312 ns) + CELL(0.340 ns) = 11.606 ns; Loc. = LC_X22_Y7_N4; Fanout = 4; COMB Node = 'code:inst1\|Selector6~279'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { code:inst1|Selector6~277 code:inst1|Selector6~279 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.088 ns) 12.683 ns code:inst1\|Mux2~29 12 COMB LC_X22_Y6_N6 3 " "Info: 12: + IC(0.989 ns) + CELL(0.088 ns) = 12.683 ns; Loc. = LC_X22_Y6_N6; Fanout = 3; COMB Node = 'code:inst1\|Mux2~29'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.077 ns" { code:inst1|Selector6~279 code:inst1|Mux2~29 } "NODE_NAME" } } { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.411 ns) + CELL(1.634 ns) 17.728 ns dataout1\[3\] 13 PIN PIN_3 0 " "Info: 13: + IC(3.411 ns) + CELL(1.634 ns) = 17.728 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'dataout1\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { code:inst1|Mux2~29 dataout1[3] } "NODE_NAME" } } { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 200 640 816 216 "dataout1\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.846 ns ( 27.34 % ) " "Info: Total cell delay = 4.846 ns ( 27.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.882 ns ( 72.66 % ) " "Info: Total interconnect delay = 12.882 ns ( 72.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "17.728 ns" { ad_control:inst|dataout[4] code:inst1|LessThan7~110 code:inst1|process0~1540 code:inst1|process0~1541 code:inst1|Selector3~230 code:inst1|Selector3~231 code:inst1|process0~1555 code:inst1|process0~1563 code:inst1|WideOr4~17 code:inst1|Selector6~277 code:inst1|Selector6~279 code:inst1|Mux2~29 dataout1[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "17.728 ns" { ad_control:inst|dataout[4] code:inst1|LessThan7~110 code:inst1|process0~1540 code:inst1|process0~1541 code:inst1|Selector3~230 code:inst1|Selector3~231 code:inst1|process0~1555 code:inst1|process0~1563 code:inst1|WideOr4~17 code:inst1|Selector6~277 code:inst1|Selector6~279 code:inst1|Mux2~29 dataout1[3] } { 0.000ns 0.926ns 0.834ns 0.528ns 1.233ns 0.850ns 1.591ns 0.322ns 0.969ns 0.917ns 0.312ns 0.989ns 3.411ns } { 0.000ns 0.088ns 0.454ns 0.340ns 0.340ns 0.454ns 0.340ns 0.340ns 0.088ns 0.340ns 0.340ns 0.088ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.516 ns" { inclk division:inst2|outclk ad_control:inst|dataout[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.516 ns" { inclk inclk~out0 division:inst2|outclk ad_control:inst|dataout[4] } { 0.000ns 0.000ns 0.430ns 2.689ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "17.728 ns" { ad_control:inst|dataout[4] code:inst1|LessThan7~110 code:inst1|process0~1540 code:inst1|process0~1541 code:inst1|Selector3~230 code:inst1|Selector3~231 code:inst1|process0~1555 code:inst1|process0~1563 code:inst1|WideOr4~17 code:inst1|Selector6~277 code:inst1|Selector6~279 code:inst1|Mux2~29 dataout1[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "17.728 ns" { ad_control:inst|dataout[4] code:inst1|LessThan7~110 code:inst1|process0~1540 code:inst1|process0~1541 code:inst1|Selector3~230 code:inst1|Selector3~231 code:inst1|process0~1555 code:inst1|process0~1563 code:inst1|WideOr4~17 code:inst1|Selector6~277 code:inst1|Selector6~279 code:inst1|Mux2~29 dataout1[3] } { 0.000ns 0.926ns 0.834ns 0.528ns 1.233ns 0.850ns 1.591ns 0.322ns 0.969ns 0.917ns 0.312ns 0.989ns 3.411ns } { 0.000ns 0.088ns 0.454ns 0.340ns 0.340ns 0.454ns 0.340ns 0.340ns 0.088ns 0.340ns 0.340ns 0.088ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}