vpc.map.qmsg

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(29) " "Warning (10492): VHDL Process Statement warning at code.vhd(29): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(30) " "Warning (10492): VHDL Process Statement warning at code.vhd(30): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(31) " "Warning (10492): VHDL Process Statement warning at code.vhd(31): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(32) " "Warning (10492): VHDL Process Statement warning at code.vhd(32): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(33) " "Warning (10492): VHDL Process Statement warning at code.vhd(33): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(34) " "Warning (10492): VHDL Process Statement warning at code.vhd(34): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(35) " "Warning (10492): VHDL Process Statement warning at code.vhd(35): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(36) " "Warning (10492): VHDL Process Statement warning at code.vhd(36): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(37) " "Warning (10492): VHDL Process Statement warning at code.vhd(37): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 37 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(38) " "Warning (10492): VHDL Process Statement warning at code.vhd(38): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 38 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp2 code.vhd(39) " "Warning (10492): VHDL Process Statement warning at code.vhd(39): signal \"temp2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 39 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ad_control:inst\|cs ad_control:inst\|rd " "Info: Duplicate register \"ad_control:inst\|cs\" merged to single register \"ad_control:inst\|rd\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 8 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|vpc\|ad_control:inst\|state 5 " "Info: State machine \"\|vpc\|ad_control:inst\|state\" contains 5 states" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|vpc\|ad_control:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|vpc\|ad_control:inst\|state\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|vpc\|ad_control:inst\|state " "Info: Encoding result for state machine \"\|vpc\|ad_control:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_control:inst\|state.s4 " "Info: Encoded state bit \"ad_control:inst\|state.s4\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_control:inst\|state.s3 " "Info: Encoded state bit \"ad_control:inst\|state.s3\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_control:inst\|state.s2 " "Info: Encoded state bit \"ad_control:inst\|state.s2\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_control:inst\|state.s1 " "Info: Encoded state bit \"ad_control:inst\|state.s1\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_control:inst\|state.s0 " "Info: Encoded state bit \"ad_control:inst\|state.s0\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vpc\|ad_control:inst\|state.s0 00000 " "Info: State \"\|vpc\|ad_control:inst\|state.s0\" uses code string \"00000\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vpc\|ad_control:inst\|state.s1 00011 " "Info: State \"\|vpc\|ad_control:inst\|state.s1\" uses code string \"00011\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vpc\|ad_control:inst\|state.s2 00101 " "Info: State \"\|vpc\|ad_control:inst\|state.s2\" uses code string \"00101\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vpc\|ad_control:inst\|state.s3 01001 " "Info: State \"\|vpc\|ad_control:inst\|state.s3\" uses code string \"01001\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|vpc\|ad_control:inst\|state.s4 10001 " "Info: State \"\|vpc\|ad_control:inst\|state.s4\" uses code string \"10001\"" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 13 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "191 " "Info: Implemented 191 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "158 " "Info: Implemented 158 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 25 21:40:03 2008 " "Info: Processing ended: Wed Jun 25 21:40:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}