vpc.map.qmsg

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 25 21:39:57 2008 " "Info: Processing started: Wed Jun 25 21:39:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vpc -c vpc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vpc -c vpc" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file division.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 division-behav " "Info: Found design unit 1: division-behav" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 division " "Info: Found entity 1: division" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "code.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file code.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 code-behav " "Info: Found design unit 1: code-behav" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 code " "Info: Found entity 1: code" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ad_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ad_control-behav " "Info: Found design unit 1: ad_control-behav" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ad_control " "Info: Found entity 1: ad_control" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vpc.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file vpc.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 vpc " "Info: Found entity 1: vpc" {  } { { "vpc.bdf" "" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vpc " "Info: Elaborating entity \"vpc\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ad_control ad_control:inst " "Info: Elaborating entity \"ad_control\" for hierarchy \"ad_control:inst\"" {  } { { "vpc.bdf" "inst" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 176 208 376 272 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "division division:inst2 " "Info: Elaborating entity \"division\" for hierarchy \"division:inst2\"" {  } { { "vpc.bdf" "inst2" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 176 40 136 272 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "code code:inst1 " "Info: Elaborating entity \"code\" for hierarchy \"code:inst1\"" {  } { { "vpc.bdf" "inst1" { Schematic "D:/altera/70/quartus/work/电压脉冲控制/vpc.bdf" { { 176 440 616 272 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(20) " "Warning (10492): VHDL Process Statement warning at code.vhd(20): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(21) " "Warning (10492): VHDL Process Statement warning at code.vhd(21): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(22) " "Warning (10492): VHDL Process Statement warning at code.vhd(22): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(23) " "Warning (10492): VHDL Process Statement warning at code.vhd(23): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(24) " "Warning (10492): VHDL Process Statement warning at code.vhd(24): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(25) " "Warning (10492): VHDL Process Statement warning at code.vhd(25): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 code.vhd(26) " "Warning (10492): VHDL Process Statement warning at code.vhd(26): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "code.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/code.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}