division.tan.qmsg

来自「电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件」· QMSG 代码 · 共 8 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[0\] register count\[5\] 364.96 MHz 2.74 ns Internal " "Info: Clock \"clk\" has Internal fmax of 364.96 MHz between source register \"count\[0\]\" and destination register \"count\[5\]\" (period= 2.74 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.538 ns + Longest register register " "Info: + Longest register to register delay is 2.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC_X9_Y12_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N9; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.434 ns) 0.837 ns Add0~120 2 COMB LC_X9_Y12_N0 2 " "Info: 2: + IC(0.403 ns) + CELL(0.434 ns) = 0.837 ns; Loc. = LC_X9_Y12_N0; Fanout = 2; COMB Node = 'Add0~120'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { count[0] Add0~120 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 0.897 ns Add0~118 3 COMB LC_X9_Y12_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 0.897 ns; Loc. = LC_X9_Y12_N1; Fanout = 2; COMB Node = 'Add0~118'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~120 Add0~118 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 0.957 ns Add0~130 4 COMB LC_X9_Y12_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 0.957 ns; Loc. = LC_X9_Y12_N2; Fanout = 2; COMB Node = 'Add0~130'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~118 Add0~130 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.017 ns Add0~128 5 COMB LC_X9_Y12_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.017 ns; Loc. = LC_X9_Y12_N3; Fanout = 2; COMB Node = 'Add0~128'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~130 Add0~128 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 1.154 ns Add0~126 6 COMB LC_X9_Y12_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 1.154 ns; Loc. = LC_X9_Y12_N4; Fanout = 3; COMB Node = 'Add0~126'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.137 ns" { Add0~128 Add0~126 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 1.632 ns Add0~123 7 COMB LC_X9_Y12_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.478 ns) = 1.632 ns; Loc. = LC_X9_Y12_N5; Fanout = 1; COMB Node = 'Add0~123'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.478 ns" { Add0~126 Add0~123 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.368 ns) 2.538 ns count\[5\] 8 REG LC_X10_Y12_N6 4 " "Info: 8: + IC(0.538 ns) + CELL(0.368 ns) = 2.538 ns; Loc. = LC_X10_Y12_N6; Fanout = 4; REG Node = 'count\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { Add0~123 count[5] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.597 ns ( 62.92 % ) " "Info: Total cell delay = 1.597 ns ( 62.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.941 ns ( 37.08 % ) " "Info: Total interconnect delay = 0.941 ns ( 37.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.538 ns" { count[0] Add0~120 Add0~118 Add0~130 Add0~128 Add0~126 Add0~123 count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.538 ns" { count[0] Add0~120 Add0~118 Add0~130 Add0~128 Add0~126 Add0~123 count[5] } { 0.000ns 0.403ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.538ns } { 0.000ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.478ns 0.368ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.129 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns count\[5\] 2 REG LC_X10_Y12_N6 4 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X10_Y12_N6; Fanout = 4; REG Node = 'count\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk count[5] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[5] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns count\[0\] 2 REG LC_X9_Y12_N9 5 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X9_Y12_N9; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk count[0] } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[5] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.538 ns" { count[0] Add0~120 Add0~118 Add0~130 Add0~128 Add0~126 Add0~123 count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.538 ns" { count[0] Add0~120 Add0~118 Add0~130 Add0~128 Add0~126 Add0~123 count[5] } { 0.000ns 0.403ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.538ns } { 0.000ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.478ns 0.368ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[5] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk outclk outclk~reg0 5.696 ns register " "Info: tco from clock \"clk\" to destination pin \"outclk\" through register \"outclk~reg0\" is 5.696 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns outclk~reg0 2 REG LC_X10_Y12_N7 1 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X10_Y12_N7; Fanout = 1; REG Node = 'outclk~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk outclk~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk outclk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 outclk~reg0 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.394 ns + Longest register pin " "Info: + Longest register to pin delay is 3.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outclk~reg0 1 REG LC_X10_Y12_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y12_N7; Fanout = 1; REG Node = 'outclk~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { outclk~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(1.622 ns) 3.394 ns outclk 2 PIN PIN_36 0 " "Info: 2: + IC(1.772 ns) + CELL(1.622 ns) = 3.394 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'outclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "division.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 47.79 % ) " "Info: Total cell delay = 1.622 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 52.21 % ) " "Info: Total interconnect delay = 1.772 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.394 ns" { outclk~reg0 outclk } { 0.000ns 1.772ns } { 0.000ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk outclk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 outclk~reg0 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.394 ns" { outclk~reg0 outclk } { 0.000ns 1.772ns } { 0.000ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 25 20:21:15 2008 " "Info: Processing ended: Wed Jun 25 20:21:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}