ad_control.tan.qmsg

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_TSU_RESULT" "dataout\[1\]~reg0 datain\[1\] clk 3.897 ns register " "Info: tsu for register \"dataout\[1\]~reg0\" (data pin = \"datain\[1\]\", clock pin = \"clk\") is 3.897 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.007 ns + Longest pin register " "Info: + Longest pin to register delay is 6.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns datain\[1\] 1 PIN PIN_48 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_48; Fanout = 1; PIN Node = 'datain\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[1] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.783 ns) + CELL(0.089 ns) 6.007 ns dataout\[1\]~reg0 2 REG LC_X26_Y10_N6 1 " "Info: 2: + IC(4.783 ns) + CELL(0.089 ns) = 6.007 ns; Loc. = LC_X26_Y10_N6; Fanout = 1; REG Node = 'dataout\[1\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.872 ns" { datain[1] dataout[1]~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 20.38 % ) " "Info: Total cell delay = 1.224 ns ( 20.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.783 ns ( 79.62 % ) " "Info: Total interconnect delay = 4.783 ns ( 79.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.007 ns" { datain[1] dataout[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.007 ns" { datain[1] datain[1]~out0 dataout[1]~reg0 } { 0.000ns 0.000ns 4.783ns } { 0.000ns 1.135ns 0.089ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 14 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns dataout\[1\]~reg0 2 REG LC_X26_Y10_N6 1 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N6; Fanout = 1; REG Node = 'dataout\[1\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk dataout[1]~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dataout[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dataout[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.007 ns" { datain[1] dataout[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.007 ns" { datain[1] datain[1]~out0 dataout[1]~reg0 } { 0.000ns 0.000ns 4.783ns } { 0.000ns 1.135ns 0.089ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dataout[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dataout[1]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rd rd~reg0 5.643 ns register " "Info: tco from clock \"clk\" to destination pin \"rd\" through register \"rd~reg0\" is 5.643 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 14 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns rd~reg0 2 REG LC_X26_Y10_N5 3 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N5; Fanout = 3; REG Node = 'rd~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk rd~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk rd~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 rd~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.331 ns + Longest register pin " "Info: + Longest register to pin delay is 3.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rd~reg0 1 REG LC_X26_Y10_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N5; Fanout = 3; REG Node = 'rd~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(1.622 ns) 3.331 ns rd 2 PIN PIN_50 0 " "Info: 2: + IC(1.709 ns) + CELL(1.622 ns) = 3.331 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'rd'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.331 ns" { rd~reg0 rd } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 48.69 % ) " "Info: Total cell delay = 1.622 ns ( 48.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.709 ns ( 51.31 % ) " "Info: Total interconnect delay = 1.709 ns ( 51.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.331 ns" { rd~reg0 rd } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.331 ns" { rd~reg0 rd } { 0.000ns 1.709ns } { 0.000ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk rd~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 rd~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.331 ns" { rd~reg0 rd } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.331 ns" { rd~reg0 rd } { 0.000ns 1.709ns } { 0.000ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dataout\[7\]~reg0 datain\[7\] clk 0.012 ns register " "Info: th for register \"dataout\[7\]~reg0\" (data pin = \"datain\[7\]\", clock pin = \"clk\") is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 14 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns dataout\[7\]~reg0 2 REG LC_X26_Y10_N8 1 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X26_Y10_N8; Fanout = 1; REG Node = 'dataout\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk dataout[7]~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dataout[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dataout[7]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.139 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns datain\[7\] 1 PIN PIN_66 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 1; PIN Node = 'datain\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[7] } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.771 ns) + CELL(0.238 ns) 2.139 ns dataout\[7\]~reg0 2 REG LC_X26_Y10_N8 1 " "Info: 2: + IC(0.771 ns) + CELL(0.238 ns) = 2.139 ns; Loc. = LC_X26_Y10_N8; Fanout = 1; REG Node = 'dataout\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { datain[7] dataout[7]~reg0 } "NODE_NAME" } } { "ad_control.vhd" "" { Text "D:/altera/70/quartus/work/电压脉冲控制/ad_control.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.368 ns ( 63.96 % ) " "Info: Total cell delay = 1.368 ns ( 63.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.771 ns ( 36.04 % ) " "Info: Total interconnect delay = 0.771 ns ( 36.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { datain[7] dataout[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { datain[7] datain[7]~out0 dataout[7]~reg0 } { 0.000ns 0.000ns 0.771ns } { 0.000ns 1.130ns 0.238ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk dataout[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 dataout[7]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { datain[7] dataout[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { datain[7] datain[7]~out0 dataout[7]~reg0 } { 0.000ns 0.000ns 0.771ns } { 0.000ns 1.130ns 0.238ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 25 20:43:13 2008 " "Info: Processing ended: Wed Jun 25 20:43:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}