vpc.fit.smsg

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 25 21:40:08 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vpc -c vpc
Info: Selected device EP1C3T100C6 for design "vpc"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 183 of 183 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 33 pins of 33 total pins
    Info: Pin cs not assigned to an exact location on the device
    Info: Pin rd not assigned to an exact location on the device
    Info: Pin dataout1[6] not assigned to an exact location on the device
    Info: Pin dataout1[5] not assigned to an exact location on the device
    Info: Pin dataout1[4] not assigned to an exact location on the device
    Info: Pin dataout1[3] not assigned to an exact location on the device
    Info: Pin dataout1[2] not assigned to an exact location on the device
    Info: Pin dataout1[1] not assigned to an exact location on the device
    Info: Pin dataout1[0] not assigned to an exact location on the device
    Info: Pin dataout2[6] not assigned to an exact location on the device
    Info: Pin dataout2[5] not assigned to an exact location on the device
    Info: Pin dataout2[4] not assigned to an exact location on the device
    Info: Pin dataout2[3] not assigned to an exact location on the device
    Info: Pin dataout2[2] not assigned to an exact location on the device
    Info: Pin dataout2[1] not assigned to an exact location on the device
    Info: Pin dataout2[0] not assigned to an exact location on the device
    Info: Pin dataout3[6] not assigned to an exact location on the device
    Info: Pin dataout3[5] not assigned to an exact location on the device
    Info: Pin dataout3[4] not assigned to an exact location on the device
    Info: Pin dataout3[3] not assigned to an exact location on the device
    Info: Pin dataout3[2] not assigned to an exact location on the device
    Info: Pin dataout3[1] not assigned to an exact location on the device
    Info: Pin dataout3[0] not assigned to an exact location on the device
    Info: Pin datain[6] not assigned to an exact location on the device
    Info: Pin datain[5] not assigned to an exact location on the device
    Info: Pin datain[4] not assigned to an exact location on the device
    Info: Pin datain[3] not assigned to an exact location on the device
    Info: Pin datain[7] not assigned to an exact location on the device
    Info: Pin datain[2] not assigned to an exact location on the device
    Info: Pin datain[1] not assigned to an exact location on the device
    Info: Pin datain[0] not assigned to an exact location on the device
    Info: Pin busy not assigned to an exact location on the device
    Info: Pin inclk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "inclk" to use Global clock in PIN 10
Info: Automatically promoted signal "division:inst2|outclk" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 32 (unused VREF, 3.30 VCCIO, 9 input, 23 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.972 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y6; Fanout = 5; REG Node = 'division:inst2|count[1]'
    Info: 2: + IC(0.536 ns) + CELL(0.443 ns) = 0.979 ns; Loc. = LAB_X9_Y6; Fanout = 2; COMB Node = 'division:inst2|Add0~126COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.041 ns; Loc. = LAB_X9_Y6; Fanout = 2; COMB Node = 'division:inst2|Add0~130COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.103 ns; Loc. = LAB_X9_Y6; Fanout = 2; COMB Node = 'division:inst2|Add0~132COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.199 ns) = 1.302 ns; Loc. = LAB_X9_Y6; Fanout = 3; COMB Node = 'division:inst2|Add0~124'
    Info: 6: + IC(0.000 ns) + CELL(0.523 ns) = 1.825 ns; Loc. = LAB_X9_Y6; Fanout = 1; COMB Node = 'division:inst2|Add0~119'
    Info: 7: + IC(0.579 ns) + CELL(0.568 ns) = 2.972 ns; Loc. = LAB_X9_Y7; Fanout = 4; REG Node = 'division:inst2|count[6]'
    Info: Total cell delay = 1.857 ns ( 62.48 % )
    Info: Total interconnect delay = 1.115 ns ( 37.52 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Wed Jun 25 21:40:13 2008
    Info: Elapsed time: 00:00:05