code.vhd

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity code is 
port(datain:in std_logic_vector(7 downto 0);
     dataout1,dataout2,dataout3:out std_logic_vector(6 downto 0));
end code;

architecture behav of code is
signal temp1:integer range 511 downto 0;
signal count1,count2:integer range 9 downto 0;
signal temp2:integer range 99 downto 0;
signal count3:integer range 5 downto 0;
begin
  process(datain)
  begin
   temp1<=conv_integer(datain)+conv_integer(datain);
   case temp1 is
     when 500 to 511=>count3<=5;temp2<=temp1-500;
     when 400 to 499=>count3<=4;temp2<=temp1-400;
     when 300 to 399=>count3<=3;temp2<=temp1-300;
     when 200 to 299=>count3<=2;temp2<=temp1-200;
     when 100 to 199=>count3<=1;temp2<=temp1-100;
     when 0 to 99=>count3<=0;temp2<=temp1;
     when others=>null;
   end case;
   case temp2 is
     when 90 to 99=>count2<=9;count1<=temp2-90;
     when 80 to 89=>count2<=8;count1<=temp2-80;
     when 70 to 79=>count2<=7;count1<=temp2-70;
     when 60 to 69=>count2<=6;count1<=temp2-60;
     when 50 to 59=>count2<=5;count1<=temp2-50;
     when 40 to 49=>count2<=4;count1<=temp2-40;
     when 30 to 39=>count2<=3;count1<=temp2-30;
     when 20 to 29=>count2<=2;count1<=temp2-20;
     when 10 to 19=>count2<=1;count1<=temp2-10;
     when 0 to 9=>count2<=0;count1<=temp2;
     when others=>null;
   end case;
  end process;
  process(count1,count2,count3)
  begin
   case count1 is
     when 0=>dataout1<="0111111";
     when 1=>dataout1<="0000110";
     when 2=>dataout1<="1011011";
     when 3=>dataout1<="1001111";
     when 4=>dataout1<="1100110";
     when 5=>dataout1<="1101101";
     when 6=>dataout1<="1111101";
     when 7=>dataout1<="0000111";
     when 8=>dataout1<="1111111";
     when 9=>dataout1<="1101111";
     when others=>null;
   end case;
   case count2 is
     when 0=>dataout2<="0111111";
     when 1=>dataout2<="0000110";
     when 2=>dataout2<="1011011";
     when 3=>dataout2<="1001111";
     when 4=>dataout2<="1100110";
     when 5=>dataout2<="1101101";
     when 6=>dataout2<="1111101";
     when 7=>dataout2<="0000111";
     when 8=>dataout2<="1111111";
     when 9=>dataout2<="1101111";
     when others=>null;
   end case; 
   case count3 is
     when 0=>dataout3<="0111111";
     when 1=>dataout3<="0000110";
     when 2=>dataout3<="1011011";
     when 3=>dataout3<="1001111";
     when 4=>dataout3<="1100110";
     when 5=>dataout3<="1101101";
     when others=>null;
   end case;
  end process;
end behav;