division.fit.smsg

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 25 20:20:56 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off division -c division
Info: Selected device EP1C3T100C6 for design "division"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 22 of 22 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin outclk not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.623 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y12; Fanout = 5; REG Node = 'count[1]'
    Info: 2: + IC(0.535 ns) + CELL(0.443 ns) = 0.978 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Add0~118COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.040 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Add0~130COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.102 ns; Loc. = LAB_X9_Y12; Fanout = 2; COMB Node = 'Add0~128COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.199 ns) = 1.301 ns; Loc. = LAB_X9_Y12; Fanout = 3; COMB Node = 'Add0~126'
    Info: 6: + IC(0.000 ns) + CELL(0.523 ns) = 1.824 ns; Loc. = LAB_X9_Y12; Fanout = 1; COMB Node = 'Add0~121'
    Info: 7: + IC(0.231 ns) + CELL(0.568 ns) = 2.623 ns; Loc. = LAB_X10_Y12; Fanout = 4; REG Node = 'count[6]'
    Info: Total cell delay = 1.857 ns ( 70.80 % )
    Info: Total interconnect delay = 0.766 ns ( 29.20 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X13_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Wed Jun 25 20:21:01 2008
    Info: Elapsed time: 00:00:05