division.vhd

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity division is
port(clk:in std_logic;
     outclk:out std_logic);
end division;

architecture behav of division is
signal count:std_logic_vector(7 downto 0);
begin
process(clk)
 begin
 if clk'event and clk='1' then
   if count=10 then
      count<="00000000";
   else  count<=count+"00000001";
   end if;
   if count<5 then 
       outclk<='0';
   else outclk<='1';
   end if;
  end if;
end process;
end behav;