📄 division.tan.rpt
字号:
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[7] ; clk ; clk ; None ; None ; 2.104 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 2.077 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; count[4] ; clk ; clk ; None ; None ; 2.067 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; count[6] ; clk ; clk ; None ; None ; 2.066 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; count[1] ; clk ; clk ; None ; None ; 2.063 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[7] ; clk ; clk ; None ; None ; 2.010 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[7] ; clk ; clk ; None ; None ; 1.976 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[7] ; clk ; clk ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[5] ; clk ; clk ; None ; None ; 1.931 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 1.926 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[7] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[7] ; clk ; clk ; None ; None ; 1.871 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[7] ; clk ; clk ; None ; None ; 1.861 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; count[3] ; clk ; clk ; None ; None ; 1.849 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; count[5] ; clk ; clk ; None ; None ; 1.842 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 1.840 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[3] ; clk ; clk ; None ; None ; 1.801 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[6] ; clk ; clk ; None ; None ; 1.788 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 1.700 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[3] ; clk ; clk ; None ; None ; 1.689 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[4] ; clk ; clk ; None ; None ; 1.667 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[0] ; clk ; clk ; None ; None ; 1.639 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[4] ; clk ; clk ; None ; None ; 1.616 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[1] ; clk ; clk ; None ; None ; 1.614 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.611 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[0] ; clk ; clk ; None ; None ; 1.531 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[0] ; clk ; clk ; None ; None ; 1.526 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[1] ; clk ; clk ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.503 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[3] ; clk ; clk ; None ; None ; 1.480 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[5] ; clk ; clk ; None ; None ; 1.479 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[0] ; clk ; clk ; None ; None ; 1.430 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[4] ; clk ; clk ; None ; None ; 1.407 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; count[1] ; clk ; clk ; None ; None ; 1.405 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[6] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.402 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.351 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[3] ; clk ; clk ; None ; None ; 1.346 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[0] ; clk ; clk ; None ; None ; 1.296 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.276 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[1] ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.268 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.236 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[7] ; outclk~reg0 ; clk ; clk ; None ; None ; 1.149 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[1] ; clk ; clk ; None ; None ; 1.121 ns ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A ; None ; 5.696 ns ; outclk~reg0 ; outclk ; clk ;
+-------+--------------+------------+-------------+--------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Wed Jun 25 20:21:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off division -c division --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 364.96 MHz between source register "count[0]" and destination register "count[5]" (period= 2.74 ns)
Info: + Longest register to register delay is 2.538 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N9; Fanout = 5; REG Node = 'count[0]'
Info: 2: + IC(0.403 ns) + CELL(0.434 ns) = 0.837 ns; Loc. = LC_X9_Y12_N0; Fanout = 2; COMB Node = 'Add0~120'
Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 0.897 ns; Loc. = LC_X9_Y12_N1; Fanout = 2; COMB Node = 'Add0~118'
Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 0.957 ns; Loc. = LC_X9_Y12_N2; Fanout = 2; COMB Node = 'Add0~130'
Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.017 ns; Loc. = LC_X9_Y12_N3; Fanout = 2; COMB Node = 'Add0~128'
Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 1.154 ns; Loc. = LC_X9_Y12_N4; Fanout = 3; COMB Node = 'Add0~126'
Info: 7: + IC(0.000 ns) + CELL(0.478 ns) = 1.632 ns; Loc. = LC_X9_Y12_N5; Fanout = 1; COMB Node = 'Add0~123'
Info: 8: + IC(0.538 ns) + CELL(0.368 ns) = 2.538 ns; Loc. = LC_X10_Y12_N6; Fanout = 4; REG Node = 'count[5]'
Info: Total cell delay = 1.597 ns ( 62.92 % )
Info: Total interconnect delay = 0.941 ns ( 37.08 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.129 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X10_Y12_N6; Fanout = 4; REG Node = 'count[5]'
Info: Total cell delay = 1.677 ns ( 78.77 % )
Info: Total interconnect delay = 0.452 ns ( 21.23 % )
Info: - Longest clock path from clock "clk" to source register is 2.129 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X9_Y12_N9; Fanout = 5; REG Node = 'count[0]'
Info: Total cell delay = 1.677 ns ( 78.77 % )
Info: Total interconnect delay = 0.452 ns ( 21.23 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "outclk" through register "outclk~reg0" is 5.696 ns
Info: + Longest clock path from clock "clk" to source register is 2.129 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X10_Y12_N7; Fanout = 1; REG Node = 'outclk~reg0'
Info: Total cell delay = 1.677 ns ( 78.77 % )
Info: Total interconnect delay = 0.452 ns ( 21.23 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 3.394 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y12_N7; Fanout = 1; REG Node = 'outclk~reg0'
Info: 2: + IC(1.772 ns) + CELL(1.622 ns) = 3.394 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'outclk'
Info: Total cell delay = 1.622 ns ( 47.79 % )
Info: Total interconnect delay = 1.772 ns ( 52.21 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 98 megabytes of memory during processing
Info: Processing ended: Wed Jun 25 20:21:15 2008
Info: Elapsed time: 00:00:02
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