dvf.tan.qmsg

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt8\[0\] register cnt8\[5\] 356.63 MHz 2.804 ns Internal " "Info: Clock \"clk\" has Internal fmax of 356.63 MHz between source register \"cnt8\[0\]\" and destination register \"cnt8\[5\]\" (period= 2.804 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.602 ns + Longest register register " "Info: + Longest register to register delay is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt8\[0\] 1 REG LC_X17_Y7_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N9; Fanout = 4; REG Node = 'cnt8\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt8[0] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.434 ns) 0.837 ns Add0~656 2 COMB LC_X17_Y7_N0 2 " "Info: 2: + IC(0.403 ns) + CELL(0.434 ns) = 0.837 ns; Loc. = LC_X17_Y7_N0; Fanout = 2; COMB Node = 'Add0~656'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { cnt8[0] Add0~656 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 0.897 ns Add0~635 3 COMB LC_X17_Y7_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 0.897 ns; Loc. = LC_X17_Y7_N1; Fanout = 2; COMB Node = 'Add0~635'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~656 Add0~635 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 0.957 ns Add0~638 4 COMB LC_X17_Y7_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 0.957 ns; Loc. = LC_X17_Y7_N2; Fanout = 2; COMB Node = 'Add0~638'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~635 Add0~638 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.017 ns Add0~641 5 COMB LC_X17_Y7_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.017 ns; Loc. = LC_X17_Y7_N3; Fanout = 2; COMB Node = 'Add0~641'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { Add0~638 Add0~641 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 1.154 ns Add0~644 6 COMB LC_X17_Y7_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 1.154 ns; Loc. = LC_X17_Y7_N4; Fanout = 3; COMB Node = 'Add0~644'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.137 ns" { Add0~641 Add0~644 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 1.632 ns Add0~646 7 COMB LC_X17_Y7_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.478 ns) = 1.632 ns; Loc. = LC_X17_Y7_N5; Fanout = 1; COMB Node = 'Add0~646'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.478 ns" { Add0~644 Add0~646 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.368 ns) 2.602 ns cnt8\[5\] 8 REG LC_X18_Y7_N2 4 " "Info: 8: + IC(0.602 ns) + CELL(0.368 ns) = 2.602 ns; Loc. = LC_X18_Y7_N2; Fanout = 4; REG Node = 'cnt8\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.970 ns" { Add0~646 cnt8[5] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.597 ns ( 61.38 % ) " "Info: Total cell delay = 1.597 ns ( 61.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.005 ns ( 38.62 % ) " "Info: Total interconnect delay = 1.005 ns ( 38.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { cnt8[0] Add0~656 Add0~635 Add0~638 Add0~641 Add0~644 Add0~646 cnt8[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { cnt8[0] Add0~656 Add0~635 Add0~638 Add0~641 Add0~644 Add0~646 cnt8[5] } { 0.000ns 0.403ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.602ns } { 0.000ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.478ns 0.368ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns cnt8\[5\] 2 REG LC_X18_Y7_N2 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N2; Fanout = 4; REG Node = 'cnt8\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk cnt8[5] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[5] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns cnt8\[0\] 2 REG LC_X17_Y7_N9 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y7_N9; Fanout = 4; REG Node = 'cnt8\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk cnt8[0] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[0] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[5] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[0] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { cnt8[0] Add0~656 Add0~635 Add0~638 Add0~641 Add0~644 Add0~646 cnt8[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { cnt8[0] Add0~656 Add0~635 Add0~638 Add0~641 Add0~644 Add0~646 cnt8[5] } { 0.000ns 0.403ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.602ns } { 0.000ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.478ns 0.368ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[5] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[0] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "cnt8\[3\] d\[3\] clk 3.998 ns register " "Info: tsu for register \"cnt8\[3\]\" (data pin = \"d\[3\]\", clock pin = \"clk\") is 3.998 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.108 ns + Longest pin register " "Info: + Longest pin to register delay is 6.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns d\[3\] 1 PIN PIN_57 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'd\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[3] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.410 ns) + CELL(0.568 ns) 6.108 ns cnt8\[3\] 2 REG LC_X18_Y7_N4 4 " "Info: 2: + IC(4.410 ns) + CELL(0.568 ns) = 6.108 ns; Loc. = LC_X18_Y7_N4; Fanout = 4; REG Node = 'cnt8\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.978 ns" { d[3] cnt8[3] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.698 ns ( 27.80 % ) " "Info: Total cell delay = 1.698 ns ( 27.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.410 ns ( 72.20 % ) " "Info: Total interconnect delay = 4.410 ns ( 72.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.108 ns" { d[3] cnt8[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.108 ns" { d[3] d[3]~out0 cnt8[3] } { 0.000ns 0.000ns 4.410ns } { 0.000ns 1.130ns 0.568ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns cnt8\[3\] 2 REG LC_X18_Y7_N4 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N4; Fanout = 4; REG Node = 'cnt8\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk cnt8[3] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[3] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.108 ns" { d[3] cnt8[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.108 ns" { d[3] d[3]~out0 cnt8[3] } { 0.000ns 0.000ns 4.410ns } { 0.000ns 1.130ns 0.568ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[3] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout fout~reg0 5.586 ns register " "Info: tco from clock \"clk\" to destination pin \"fout\" through register \"fout~reg0\" is 5.586 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns fout~reg0 2 REG LC_X18_Y7_N8 2 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N8; Fanout = 2; REG Node = 'fout~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk fout~reg0 } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk fout~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.274 ns + Longest register pin " "Info: + Longest register to pin delay is 3.274 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fout~reg0 1 REG LC_X18_Y7_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y7_N8; Fanout = 2; REG Node = 'fout~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fout~reg0 } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.652 ns) + CELL(1.622 ns) 3.274 ns fout 2 PIN PIN_42 0 " "Info: 2: + IC(1.652 ns) + CELL(1.622 ns) = 3.274 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'fout'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.274 ns" { fout~reg0 fout } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 49.54 % ) " "Info: Total cell delay = 1.622 ns ( 49.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.652 ns ( 50.46 % ) " "Info: Total interconnect delay = 1.652 ns ( 50.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.274 ns" { fout~reg0 fout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.274 ns" { fout~reg0 fout } { 0.000ns 1.652ns } { 0.000ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk fout~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.274 ns" { fout~reg0 fout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.274 ns" { fout~reg0 fout } { 0.000ns 1.652ns } { 0.000ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "cnt8\[1\] d\[1\] clk -3.666 ns register " "Info: th for register \"cnt8\[1\]\" (data pin = \"d\[1\]\", clock pin = \"clk\") is -3.666 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns cnt8\[1\] 2 REG LC_X18_Y7_N9 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N9; Fanout = 4; REG Node = 'cnt8\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { clk cnt8[1] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.817 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns d\[1\] 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'd\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[1] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.215 ns) + CELL(0.467 ns) 5.817 ns cnt8\[1\] 2 REG LC_X18_Y7_N9 4 " "Info: 2: + IC(4.215 ns) + CELL(0.467 ns) = 5.817 ns; Loc. = LC_X18_Y7_N9; Fanout = 4; REG Node = 'cnt8\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.682 ns" { d[1] cnt8[1] } "NODE_NAME" } } { "dvf.vhd" "" { Text "D:/altera/70/quartus/work/dvf(数控分频器)/dvf.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.602 ns ( 27.54 % ) " "Info: Total cell delay = 1.602 ns ( 27.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.215 ns ( 72.46 % ) " "Info: Total interconnect delay = 4.215 ns ( 72.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.817 ns" { d[1] cnt8[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.817 ns" { d[1] d[1]~out0 cnt8[1] } { 0.000ns 0.000ns 4.215ns } { 0.000ns 1.135ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { clk cnt8[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 cnt8[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.817 ns" { d[1] cnt8[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.817 ns" { d[1] d[1]~out0 cnt8[1] } { 0.000ns 0.000ns 4.215ns } { 0.000ns 1.135ns 0.467ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}