dvf.tan.rpt

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件

; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[2]   ; cnt8[1]   ; clk        ; clk      ; None                        ; None                      ; 1.760 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[2]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.758 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[2]   ; cnt8[2]   ; clk        ; clk      ; None                        ; None                      ; 1.756 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[6]   ; cnt8[0]   ; clk        ; clk      ; None                        ; None                      ; 1.739 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[0]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.698 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[3]   ; cnt8[1]   ; clk        ; clk      ; None                        ; None                      ; 1.679 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[3]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.677 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[3]   ; cnt8[2]   ; clk        ; clk      ; None                        ; None                      ; 1.675 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[1]   ; cnt8[0]   ; clk        ; clk      ; None                        ; None                      ; 1.644 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[2]   ; cnt8[0]   ; clk        ; clk      ; None                        ; None                      ; 1.515 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[0]   ; cnt8[0]   ; clk        ; clk      ; None                        ; None                      ; 1.455 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[3]   ; cnt8[0]   ; clk        ; clk      ; None                        ; None                      ; 1.434 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[5]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.429 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[7]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.393 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[4]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.302 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[5]   ; cnt8[3]   ; clk        ; clk      ; None                        ; None                      ; 1.238 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[7]   ; cnt8[3]   ; clk        ; clk      ; None                        ; None                      ; 1.202 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[4]   ; cnt8[3]   ; clk        ; clk      ; None                        ; None                      ; 1.111 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[6]   ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.053 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; cnt8[6]   ; cnt8[3]   ; clk        ; clk      ; None                        ; None                      ; 0.862 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; fout~reg0 ; fout~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.861 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tsu                                                           ;
+-------+--------------+------------+------+---------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To      ; To Clock ;
+-------+--------------+------------+------+---------+----------+
; N/A   ; None         ; 3.998 ns   ; d[3] ; cnt8[3] ; clk      ;
; N/A   ; None         ; 3.839 ns   ; d[6] ; cnt8[6] ; clk      ;
; N/A   ; None         ; 3.818 ns   ; d[0] ; cnt8[0] ; clk      ;
; N/A   ; None         ; 3.783 ns   ; d[4] ; cnt8[4] ; clk      ;
; N/A   ; None         ; 3.746 ns   ; d[5] ; cnt8[5] ; clk      ;
; N/A   ; None         ; 3.720 ns   ; d[2] ; cnt8[2] ; clk      ;
; N/A   ; None         ; 3.718 ns   ; d[7] ; cnt8[7] ; clk      ;
; N/A   ; None         ; 3.707 ns   ; d[1] ; cnt8[1] ; clk      ;
+-------+--------------+------------+------+---------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 5.586 ns   ; fout~reg0 ; fout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; -3.666 ns ; d[1] ; cnt8[1] ; clk      ;
; N/A           ; None        ; -3.677 ns ; d[7] ; cnt8[7] ; clk      ;
; N/A           ; None        ; -3.679 ns ; d[2] ; cnt8[2] ; clk      ;
; N/A           ; None        ; -3.705 ns ; d[5] ; cnt8[5] ; clk      ;
; N/A           ; None        ; -3.742 ns ; d[4] ; cnt8[4] ; clk      ;
; N/A           ; None        ; -3.777 ns ; d[0] ; cnt8[0] ; clk      ;
; N/A           ; None        ; -3.798 ns ; d[6] ; cnt8[6] ; clk      ;
; N/A           ; None        ; -3.957 ns ; d[3] ; cnt8[3] ; clk      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Jun 22 20:56:36 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dvf -c dvf --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 356.63 MHz between source register "cnt8[0]" and destination register "cnt8[5]" (period= 2.804 ns)
    Info: + Longest register to register delay is 2.602 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N9; Fanout = 4; REG Node = 'cnt8[0]'
        Info: 2: + IC(0.403 ns) + CELL(0.434 ns) = 0.837 ns; Loc. = LC_X17_Y7_N0; Fanout = 2; COMB Node = 'Add0~656'
        Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 0.897 ns; Loc. = LC_X17_Y7_N1; Fanout = 2; COMB Node = 'Add0~635'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 0.957 ns; Loc. = LC_X17_Y7_N2; Fanout = 2; COMB Node = 'Add0~638'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.017 ns; Loc. = LC_X17_Y7_N3; Fanout = 2; COMB Node = 'Add0~641'
        Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 1.154 ns; Loc. = LC_X17_Y7_N4; Fanout = 3; COMB Node = 'Add0~644'
        Info: 7: + IC(0.000 ns) + CELL(0.478 ns) = 1.632 ns; Loc. = LC_X17_Y7_N5; Fanout = 1; COMB Node = 'Add0~646'
        Info: 8: + IC(0.602 ns) + CELL(0.368 ns) = 2.602 ns; Loc. = LC_X18_Y7_N2; Fanout = 4; REG Node = 'cnt8[5]'
        Info: Total cell delay = 1.597 ns ( 61.38 % )
        Info: Total interconnect delay = 1.005 ns ( 38.62 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.139 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N2; Fanout = 4; REG Node = 'cnt8[5]'
            Info: Total cell delay = 1.677 ns ( 78.40 % )
            Info: Total interconnect delay = 0.462 ns ( 21.60 % )
        Info: - Longest clock path from clock "clk" to source register is 2.139 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X17_Y7_N9; Fanout = 4; REG Node = 'cnt8[0]'
            Info: Total cell delay = 1.677 ns ( 78.40 % )
            Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "cnt8[3]" (data pin = "d[3]", clock pin = "clk") is 3.998 ns
    Info: + Longest pin to register delay is 6.108 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'd[3]'
        Info: 2: + IC(4.410 ns) + CELL(0.568 ns) = 6.108 ns; Loc. = LC_X18_Y7_N4; Fanout = 4; REG Node = 'cnt8[3]'
        Info: Total cell delay = 1.698 ns ( 27.80 % )
        Info: Total interconnect delay = 4.410 ns ( 72.20 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N4; Fanout = 4; REG Node = 'cnt8[3]'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
Info: tco from clock "clk" to destination pin "fout" through register "fout~reg0" is 5.586 ns
    Info: + Longest clock path from clock "clk" to source register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N8; Fanout = 2; REG Node = 'fout~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.274 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y7_N8; Fanout = 2; REG Node = 'fout~reg0'
        Info: 2: + IC(1.652 ns) + CELL(1.622 ns) = 3.274 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'fout'
        Info: Total cell delay = 1.622 ns ( 49.54 % )
        Info: Total interconnect delay = 1.652 ns ( 50.46 % )
Info: th for register "cnt8[1]" (data pin = "d[1]", clock pin = "clk") is -3.666 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X18_Y7_N9; Fanout = 4; REG Node = 'cnt8[1]'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.817 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'd[1]'
        Info: 2: + IC(4.215 ns) + CELL(0.467 ns) = 5.817 ns; Loc. = LC_X18_Y7_N9; Fanout = 4; REG Node = 'cnt8[1]'
        Info: Total cell delay = 1.602 ns ( 27.54 % )
        Info: Total interconnect delay = 4.215 ns ( 72.46 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Sun Jun 22 20:56:38 2008
    Info: Elapsed time: 00:00:02