dvf.fit.rpt

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件

; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:3     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:3     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:3     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:3     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:3     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:3     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:3     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:3     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:3     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:3     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:3     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:3     ;
; LEs in Chains - Fit Attempt 1                                                  ; 8       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0       ;
; LABs with Chains - Fit Attempt 1                                               ; 1       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff    ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Early Slack - Fit Attempt 1         ; -3087 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff    ;
; Mid Wire Use - Fit Attempt 1        ; 0     ;
; Mid Slack - Fit Attempt 1           ; -3087 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Late Slack - Fit Attempt 1          ; -3087 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff    ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -2268 ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 0     ;
; Mid Slack - Fit Attempt 1           ; -2293 ;
; Late Slack - Fit Attempt 1          ; -2293 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.079 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Jun 22 20:56:17 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dvf -c dvf
Info: Automatically selected device EP1C3T100C6 for design dvf
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 29 of 29 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 10 pins of 10 total pins
    Info: Pin fout not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin d[0] not assigned to an exact location on the device
    Info: Pin d[1] not assigned to an exact location on the device
    Info: Pin d[2] not assigned to an exact location on the device
    Info: Pin d[3] not assigned to an exact location on the device
    Info: Pin d[4] not assigned to an exact location on the device
    Info: Pin d[5] not assigned to an exact location on the device
    Info: Pin d[6] not assigned to an exact location on the device
    Info: Pin d[7] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 9 (unused VREF, 3.30 VCCIO, 8 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.636 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y7; Fanout = 4; REG Node = 'cnt8[1]'
    Info: 2: + IC(0.535 ns) + CELL(0.443 ns) = 0.978 ns; Loc. = LAB_X17_Y7; Fanout = 2; COMB Node = 'Add0~635COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.040 ns; Loc. = LAB_X17_Y7; Fanout = 2; COMB Node = 'Add0~638COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.102 ns; Loc. = LAB_X17_Y7; Fanout = 2; COMB Node = 'Add0~641COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.199 ns) = 1.301 ns; Loc. = LAB_X17_Y7; Fanout = 3; COMB Node = 'Add0~644'
    Info: 6: + IC(0.000 ns) + CELL(0.523 ns) = 1.824 ns; Loc. = LAB_X17_Y7; Fanout = 1; COMB Node = 'Add0~646'
    Info: 7: + IC(0.345 ns) + CELL(0.467 ns) = 2.636 ns; Loc. = LAB_X18_Y7; Fanout = 4; REG Node = 'cnt8[5]'
    Info: Total cell delay = 1.756 ns ( 66.62 % )
    Info: Total interconnect delay = 0.880 ns ( 33.38 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Sun Jun 22 20:56:23 2008
    Info: Elapsed time: 00:00:06


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/altera/70/quartus/work/dvf(数控分频器)/dvf.fit.smsg.