adcint.tan.qmsg

模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_TH_RESULT" "regl\[6\] d\[6\] clk 3.962 ns register " "Info: th for register \"regl\[6\]\" (data pin = \"d\[6\]\", clock pin = \"clk\") is 3.962 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.938 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.720 ns) 2.302 ns current_state.st4 2 REG LC_X7_Y10_N0 11 " "Info: 2: + IC(0.452 ns) + CELL(0.720 ns) = 2.302 ns; Loc. = LC_X7_Y10_N0; Fanout = 11; REG Node = 'current_state.st4'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.172 ns" { clk current_state.st4 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.089 ns) + CELL(0.547 ns) 5.938 ns regl\[6\] 3 REG LC_X26_Y8_N2 1 " "Info: 3: + IC(3.089 ns) + CELL(0.547 ns) = 5.938 ns; Loc. = LC_X26_Y8_N2; Fanout = 1; REG Node = 'regl\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.636 ns" { current_state.st4 regl[6] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 40.37 % ) " "Info: Total cell delay = 2.397 ns ( 40.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.541 ns ( 59.63 % ) " "Info: Total interconnect delay = 3.541 ns ( 59.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.938 ns" { clk current_state.st4 regl[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.938 ns" { clk clk~out0 current_state.st4 regl[6] } { 0.000ns 0.000ns 0.452ns 3.089ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.988 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns d\[6\] 1 PIN PIN_66 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 1; PIN Node = 'd\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[6] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.089 ns) 1.988 ns regl\[6\] 2 REG LC_X26_Y8_N2 1 " "Info: 2: + IC(0.769 ns) + CELL(0.089 ns) = 1.988 ns; Loc. = LC_X26_Y8_N2; Fanout = 1; REG Node = 'regl\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.858 ns" { d[6] regl[6] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns ( 61.32 % ) " "Info: Total cell delay = 1.219 ns ( 61.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.769 ns ( 38.68 % ) " "Info: Total interconnect delay = 0.769 ns ( 38.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.988 ns" { d[6] regl[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.988 ns" { d[6] d[6]~out0 regl[6] } { 0.000ns 0.000ns 0.769ns } { 0.000ns 1.130ns 0.089ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.938 ns" { clk current_state.st4 regl[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.938 ns" { clk clk~out0 current_state.st4 regl[6] } { 0.000ns 0.000ns 0.452ns 3.089ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.988 ns" { d[6] regl[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.988 ns" { d[6] d[6]~out0 regl[6] } { 0.000ns 0.000ns 0.769ns } { 0.000ns 1.130ns 0.089ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 15:39:27 2008 " "Info: Processing ended: Wed May 07 15:39:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}