📄 adcint.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st4 " "Info: Detected ripple clock \"current_state.st4\" as buffer" { } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "current_state.st4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register current_state.st1 current_state.st2 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"current_state.st1\" and destination register \"current_state.st2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.789 ns + Longest register register " "Info: + Longest register to register delay is 0.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st1 1 REG LC_X7_Y10_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y10_N9; Fanout = 3; REG Node = 'current_state.st1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.st1 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.368 ns) 0.789 ns current_state.st2 2 REG LC_X7_Y10_N3 2 " "Info: 2: + IC(0.421 ns) + CELL(0.368 ns) = 0.789 ns; Loc. = LC_X7_Y10_N3; Fanout = 2; REG Node = 'current_state.st2'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { current_state.st1 current_state.st2 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.368 ns ( 46.64 % ) " "Info: Total cell delay = 0.368 ns ( 46.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.421 ns ( 53.36 % ) " "Info: Total interconnect delay = 0.421 ns ( 53.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { current_state.st1 current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.789 ns" { current_state.st1 current_state.st2 } { 0.000ns 0.421ns } { 0.000ns 0.368ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.129 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns current_state.st2 2 REG LC_X7_Y10_N3 2 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N3; Fanout = 2; REG Node = 'current_state.st2'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk current_state.st2 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st2 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns current_state.st1 2 REG LC_X7_Y10_N9 3 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N9; Fanout = 3; REG Node = 'current_state.st1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk current_state.st1 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st1 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st2 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st1 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.789 ns" { current_state.st1 current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.789 ns" { current_state.st1 current_state.st2 } { 0.000ns 0.421ns } { 0.000ns 0.368ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st2 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st1 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { current_state.st2 } { } { } "" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st3 eoc clk 3.394 ns register " "Info: tsu for register \"current_state.st3\" (data pin = \"eoc\", clock pin = \"clk\") is 3.394 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.494 ns + Longest pin register " "Info: + Longest pin to register delay is 5.494 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns eoc 1 PIN PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'eoc'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.892 ns) + CELL(0.467 ns) 5.494 ns current_state.st3 2 REG LC_X7_Y10_N2 2 " "Info: 2: + IC(3.892 ns) + CELL(0.467 ns) = 5.494 ns; Loc. = LC_X7_Y10_N2; Fanout = 2; REG Node = 'current_state.st3'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.359 ns" { eoc current_state.st3 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.602 ns ( 29.16 % ) " "Info: Total cell delay = 1.602 ns ( 29.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.892 ns ( 70.84 % ) " "Info: Total interconnect delay = 3.892 ns ( 70.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.494 ns" { eoc current_state.st3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.494 ns" { eoc eoc~out0 current_state.st3 } { 0.000ns 0.000ns 3.892ns } { 0.000ns 1.135ns 0.467ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.129 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns current_state.st3 2 REG LC_X7_Y10_N2 2 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N2; Fanout = 2; REG Node = 'current_state.st3'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk current_state.st3 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st3 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.494 ns" { eoc current_state.st3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.494 ns" { eoc eoc~out0 current_state.st3 } { 0.000ns 0.000ns 3.892ns } { 0.000ns 1.135ns 0.467ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk current_state.st3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk clk~out0 current_state.st3 } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[5\] regl\[5\] 9.374 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[5\]\" through register \"regl\[5\]\" is 9.374 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.926 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.720 ns) 2.302 ns current_state.st4 2 REG LC_X7_Y10_N0 11 " "Info: 2: + IC(0.452 ns) + CELL(0.720 ns) = 2.302 ns; Loc. = LC_X7_Y10_N0; Fanout = 11; REG Node = 'current_state.st4'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.172 ns" { clk current_state.st4 } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.077 ns) + CELL(0.547 ns) 5.926 ns regl\[5\] 3 REG LC_X10_Y9_N2 1 " "Info: 3: + IC(3.077 ns) + CELL(0.547 ns) = 5.926 ns; Loc. = LC_X10_Y9_N2; Fanout = 1; REG Node = 'regl\[5\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.624 ns" { current_state.st4 regl[5] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 40.45 % ) " "Info: Total cell delay = 2.397 ns ( 40.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.529 ns ( 59.55 % ) " "Info: Total interconnect delay = 3.529 ns ( 59.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.926 ns" { clk current_state.st4 regl[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.926 ns" { clk clk~out0 current_state.st4 regl[5] } { 0.000ns 0.000ns 0.452ns 3.077ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.275 ns + Longest register pin " "Info: + Longest register to pin delay is 3.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns regl\[5\] 1 REG LC_X10_Y9_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N2; Fanout = 1; REG Node = 'regl\[5\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { regl[5] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(1.622 ns) 3.275 ns q\[5\] 2 PIN PIN_36 0 " "Info: 2: + IC(1.653 ns) + CELL(1.622 ns) = 3.275 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'q\[5\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.275 ns" { regl[5] q[5] } "NODE_NAME" } } { "adcint.vhd" "" { Text "D:/altera/70/quartus/work/ADCINT/adcint.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 49.53 % ) " "Info: Total cell delay = 1.622 ns ( 49.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns ( 50.47 % ) " "Info: Total interconnect delay = 1.653 ns ( 50.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.275 ns" { regl[5] q[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.275 ns" { regl[5] q[5] } { 0.000ns 1.653ns } { 0.000ns 1.622ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.926 ns" { clk current_state.st4 regl[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.926 ns" { clk clk~out0 current_state.st4 regl[5] } { 0.000ns 0.000ns 0.452ns 3.077ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.275 ns" { regl[5] q[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.275 ns" { regl[5] q[5] } { 0.000ns 1.653ns } { 0.000ns 1.622ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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