adcint.tan.rpt

模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件

+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+-------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To    ; From Clock ;
+-------+--------------+------------+-------------------+-------+------------+
; N/A   ; None         ; 9.374 ns   ; regl[5]           ; q[5]  ; clk        ;
; N/A   ; None         ; 9.057 ns   ; regl[7]           ; q[7]  ; clk        ;
; N/A   ; None         ; 8.964 ns   ; regl[0]           ; q[0]  ; clk        ;
; N/A   ; None         ; 8.725 ns   ; regl[2]           ; q[2]  ; clk        ;
; N/A   ; None         ; 8.724 ns   ; regl[4]           ; q[4]  ; clk        ;
; N/A   ; None         ; 8.713 ns   ; regl[1]           ; q[1]  ; clk        ;
; N/A   ; None         ; 8.619 ns   ; regl[6]           ; q[6]  ; clk        ;
; N/A   ; None         ; 8.619 ns   ; regl[3]           ; q[3]  ; clk        ;
; N/A   ; None         ; 6.465 ns   ; current_state.st3 ; oe    ; clk        ;
; N/A   ; None         ; 6.152 ns   ; current_state.st1 ; start ; clk        ;
; N/A   ; None         ; 5.876 ns   ; current_state.st4 ; oe    ; clk        ;
; N/A   ; None         ; 5.619 ns   ; current_state.st4 ; locko ; clk        ;
; N/A   ; None         ; 5.296 ns   ; current_state.st1 ; ale   ; clk        ;
+-------+--------------+------------+-------------------+-------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 3.962 ns  ; d[6] ; regl[6]           ; clk      ;
; N/A           ; None        ; 1.205 ns  ; d[1] ; regl[1]           ; clk      ;
; N/A           ; None        ; 0.865 ns  ; d[3] ; regl[3]           ; clk      ;
; N/A           ; None        ; 0.731 ns  ; d[2] ; regl[2]           ; clk      ;
; N/A           ; None        ; 0.731 ns  ; d[0] ; regl[0]           ; clk      ;
; N/A           ; None        ; 0.659 ns  ; d[7] ; regl[7]           ; clk      ;
; N/A           ; None        ; 0.618 ns  ; d[4] ; regl[4]           ; clk      ;
; N/A           ; None        ; 0.521 ns  ; d[5] ; regl[5]           ; clk      ;
; N/A           ; None        ; -3.353 ns ; eoc  ; current_state.st3 ; clk      ;
; N/A           ; None        ; -3.353 ns ; eoc  ; current_state.st2 ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed May 07 15:39:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adcint -c adcint --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.st4" as buffer
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "current_state.st1" and destination register "current_state.st2"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.789 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y10_N9; Fanout = 3; REG Node = 'current_state.st1'
            Info: 2: + IC(0.421 ns) + CELL(0.368 ns) = 0.789 ns; Loc. = LC_X7_Y10_N3; Fanout = 2; REG Node = 'current_state.st2'
            Info: Total cell delay = 0.368 ns ( 46.64 % )
            Info: Total interconnect delay = 0.421 ns ( 53.36 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.129 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N3; Fanout = 2; REG Node = 'current_state.st2'
                Info: Total cell delay = 1.677 ns ( 78.77 % )
                Info: Total interconnect delay = 0.452 ns ( 21.23 % )
            Info: - Longest clock path from clock "clk" to source register is 2.129 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N9; Fanout = 3; REG Node = 'current_state.st1'
                Info: Total cell delay = 1.677 ns ( 78.77 % )
                Info: Total interconnect delay = 0.452 ns ( 21.23 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "current_state.st3" (data pin = "eoc", clock pin = "clk") is 3.394 ns
    Info: + Longest pin to register delay is 5.494 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'eoc'
        Info: 2: + IC(3.892 ns) + CELL(0.467 ns) = 5.494 ns; Loc. = LC_X7_Y10_N2; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 1.602 ns ( 29.16 % )
        Info: Total interconnect delay = 3.892 ns ( 70.84 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.129 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X7_Y10_N2; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 1.677 ns ( 78.77 % )
        Info: Total interconnect delay = 0.452 ns ( 21.23 % )
Info: tco from clock "clk" to destination pin "q[5]" through register "regl[5]" is 9.374 ns
    Info: + Longest clock path from clock "clk" to source register is 5.926 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.452 ns) + CELL(0.720 ns) = 2.302 ns; Loc. = LC_X7_Y10_N0; Fanout = 11; REG Node = 'current_state.st4'
        Info: 3: + IC(3.077 ns) + CELL(0.547 ns) = 5.926 ns; Loc. = LC_X10_Y9_N2; Fanout = 1; REG Node = 'regl[5]'
        Info: Total cell delay = 2.397 ns ( 40.45 % )
        Info: Total interconnect delay = 3.529 ns ( 59.55 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.275 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N2; Fanout = 1; REG Node = 'regl[5]'
        Info: 2: + IC(1.653 ns) + CELL(1.622 ns) = 3.275 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'q[5]'
        Info: Total cell delay = 1.622 ns ( 49.53 % )
        Info: Total interconnect delay = 1.653 ns ( 50.47 % )
Info: th for register "regl[6]" (data pin = "d[6]", clock pin = "clk") is 3.962 ns
    Info: + Longest clock path from clock "clk" to destination register is 5.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.452 ns) + CELL(0.720 ns) = 2.302 ns; Loc. = LC_X7_Y10_N0; Fanout = 11; REG Node = 'current_state.st4'
        Info: 3: + IC(3.089 ns) + CELL(0.547 ns) = 5.938 ns; Loc. = LC_X26_Y8_N2; Fanout = 1; REG Node = 'regl[6]'
        Info: Total cell delay = 2.397 ns ( 40.37 % )
        Info: Total interconnect delay = 3.541 ns ( 59.63 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 1.988 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 1; PIN Node = 'd[6]'
        Info: 2: + IC(0.769 ns) + CELL(0.089 ns) = 1.988 ns; Loc. = LC_X26_Y8_N2; Fanout = 1; REG Node = 'regl[6]'
        Info: Total cell delay = 1.219 ns ( 61.32 % )
        Info: Total interconnect delay = 0.769 ns ( 38.68 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Wed May 07 15:39:27 2008
    Info: Elapsed time: 00:00:01