adcint.fit.rpt

模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件

; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff      ;
; Mid Wire Use - Fit Attempt 1                                                   ; 0       ;
; Mid Slack - Fit Attempt 1                                                      ; -2667   ;
; Internal Atom Count - Fit Attempt 1                                            ; 14      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 14      ;
; LAB Count - Fit Attempt 1                                                      ; 10      ;
; Outputs per Lab - Fit Attempt 1                                                ; 1.100   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 1.000   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.900   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:10    ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:10    ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:10    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:10    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:10    ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:10    ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:10    ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:10    ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:10    ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:9 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:9 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:10    ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:9 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:9;1:1 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:10    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:10    ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:10    ;
; LEs in Chains - Fit Attempt 1                                                  ; 0       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0       ;
; LABs with Chains - Fit Attempt 1                                               ; 0       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff    ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Early Slack - Fit Attempt 1         ; -1140 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff    ;
; Mid Wire Use - Fit Attempt 1        ; 0     ;
; Mid Slack - Fit Attempt 1           ; -1140 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Late Slack - Fit Attempt 1          ; -1140 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff    ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 0     ;
; Early Slack - Fit Attempt 1         ; -314  ;
; Mid Slack - Fit Attempt 1           ; -402  ;
; Late Slack - Fit Attempt 1          ; -402  ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed May 07 15:39:07 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adcint -c adcint
Info: Automatically selected device EP1C3T100C6 for design adcint
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 37 of 37 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 23 pins of 23 total pins
    Info: Pin ale not assigned to an exact location on the device
    Info: Pin start not assigned to an exact location on the device
    Info: Pin oe not assigned to an exact location on the device
    Info: Pin adda not assigned to an exact location on the device
    Info: Pin locko not assigned to an exact location on the device
    Info: Pin q[0] not assigned to an exact location on the device
    Info: Pin q[1] not assigned to an exact location on the device
    Info: Pin q[2] not assigned to an exact location on the device
    Info: Pin q[3] not assigned to an exact location on the device
    Info: Pin q[4] not assigned to an exact location on the device
    Info: Pin q[5] not assigned to an exact location on the device
    Info: Pin q[6] not assigned to an exact location on the device
    Info: Pin q[7] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin eoc not assigned to an exact location on the device
    Info: Pin d[0] not assigned to an exact location on the device
    Info: Pin d[1] not assigned to an exact location on the device
    Info: Pin d[2] not assigned to an exact location on the device
    Info: Pin d[3] not assigned to an exact location on the device
    Info: Pin d[4] not assigned to an exact location on the device
    Info: Pin d[5] not assigned to an exact location on the device
    Info: Pin d[6] not assigned to an exact location on the device
    Info: Pin d[7] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Automatically promoted some destinations of signal "current_state.st4" to use Global clock
    Info: Destination "oe~0" may be non-global or may not use global clock
    Info: Destination "current_state.st0" may be non-global or may not use global clock
    Info: Destination "locko" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 9 input, 13 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pi