adcint.vhd

模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
entity adcint is
 port(d:std_logic_vector(7 downto 0);
      clk:in std_logic;
      eoc:in std_logic;
      ale:out std_logic;
      start:out std_logic;
      oe:out std_logic;
      adda:out std_logic;
      locko:out std_logic;
      q:out std_logic_vector(7 downto 0));
end adcint;

architecture behav of adcint is
 type states is(st0,st1,st2,st3,st4);
  signal current_state,next_state:states;
  signal regl:std_logic_vector(7 downto 0);
  signal lock:std_logic;
 begin
 q<=regl;
 locko<=lock;
 adda<='1';
 REG:process(clk)
   begin
     if clk'event and clk='1' then
        current_state<=next_state;
     end if;
   end process REG;
 COM:process(current_state,eoc)
   begin
     case current_state is
       when st0=>start<='0';oe<='0'; lock<='0';ale<='0';next_state<=st1;
       when st1=>start<='1';oe<='0'; lock<='0';ale<='1';next_state<=st2;
       when st2=>start<='0';oe<='0'; lock<='0';ale<='0';
           if eoc='1' then next_state<=st3;
           else next_state<=st2;
           end if;
       when st3=>start<='0';oe<='1'; lock<='0';ale<='0';next_state<=st4;
       when st4=>start<='0';oe<='1'; lock<='1';ale<='0';next_state<=st0;
       when others=>next_state<=st0;
     end case;
   end process COM;
 LATCH1:process(lock)
    begin
    if lock'event and lock='1' then
      regl<=d;
    end if;
 end process LATCH1;


 end behav;