📄 mdm_core.vhd
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signal read_RX_FIFO : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal rx_Data_Present : std_logic;
signal rx_BUFFER_FULL : std_logic;
signal write_TX_FIFO : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_BUFFER_FULL : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal xfer_Ack : std_logic;
signal mdm_Dbus_i : std_logic_vector(DBUS_START to 31);
signal mdm_CS : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_1 : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_2 : std_logic; -- Active only 1 clock cycle during an
signal mdm_CS_3 : std_logic; -- Active only 1 clock cycle during an
-- access
signal opb_RNW_1 : std_logic;
constant C_AWIDTH : natural := 32;
function Addr_Bits (x, y : std_logic_vector(0 to C_AWIDTH-1)) return integer is
variable addr_nor : std_logic_vector(0 to C_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_AWIDTH-1 loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return(C_AWIDTH);
end function Addr_Bits;
constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);
signal MB_Debug_Enabled : std_logic_vector(0 to C_EN_WIDTH-1); -- [out]
signal Dbg_Clk : std_logic; -- [out]
signal Dbg_TDI : std_logic; -- [out]
signal Dbg_TDO : std_logic; -- [in]
signal Dbg_Reg_En : std_logic_vector(0 to 4); -- [out]
signal Dbg_Capture : std_logic; -- [out]
signal Dbg_Update : std_logic; -- [out]
subtype Reg_En_TYPE is std_logic_vector(0 to 4);
type Reg_EN_ARRAY is array(0 to 7) of Reg_En_TYPE;
signal Dbg_TDO_I : std_logic_vector(0 to 7);
signal Dbg_TDI_I : std_logic_vector(0 to 7);
signal Dbg_Reg_En_I : Reg_EN_ARRAY;
signal Dbg_Capture_I : std_logic_vector(0 to 7);
signal Dbg_Update_I : std_logic_vector(0 to 7);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the OPB bus interface
-----------------------------------------------------------------------------
-- Do the OPB address decoding
pselect_I : pselect
generic map (
C_AB => C_AB, -- [integer]
C_AW => OPB_ABus'length, -- [integer]
C_BAR => C_BASEADDR) -- [std_logic_vector]
port map (
A => OPB_ABus, -- [in std_logic_vector(0 to C_AW-1)]
AValid => OPB_select, -- [in std_logic]
cs => mdm_CS); -- [out std_logic]
MDM_errAck <= '0';
MDM_retry <= '0';
MDM_toutSup <= '0';
mdm_CS_1_DFF : FDR
port map (
Q => mdm_CS_1, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
D => MDM_CS, -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
mdm_CS_2_DFF : process (OPB_Clk, OPB_Rst) is
begin -- process mdm_CS_2_DFF
if OPB_Rst = '1' then -- asynchronous reset (active high)
mdm_CS_2 <= '0';
mdm_CS_3 <= '0';
opb_RNW_1 <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
mdm_CS_2 <= mdm_CS_1 and not mdm_CS_2 and not mdm_CS_3;
mdm_CS_3 <= mdm_CS_2;
opb_RNW_1 <= OPB_RNW;
end if;
end process mdm_CS_2_DFF;
-----------------------------------------------------------------------------
-- Status register handling
-----------------------------------------------------------------------------
status_Reg(7) <= rx_Data_Present;
status_Reg(6) <= rx_BUFFER_FULL;
status_Reg(5) <= tx_Buffer_Empty;
status_Reg(4) <= tx_BUFFER_FULL;
status_Reg(3) <= enable_interrupts;
status_Reg(0 to 2) <= "000";
-----------------------------------------------------------------------------
-- Control Register Handling
-----------------------------------------------------------------------------
Ctrl_Reg_DFF : process (OPB_Clk, OPB_Rst) is
begin -- process Ctrl_Reg_DFF
if OPB_Rst = '1' then -- asynchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
clear_Ext_BRK <= '0';
if (mdm_CS_2 = '1') and (OPB_RNW_1 = '0') and (OPB_ABus(28 to 29) = CTRL_REG_ADR) then
reset_RX_FIFO <= OPB_DBus(30);
reset_TX_FIFO <= OPB_DBus(31);
enable_interrupts <= OPB_DBus(27);
clear_Ext_BRK <= OPB_DBus(29);
end if;
end if;
end process Ctrl_Reg_DFF;
-----------------------------------------------------------------------------
-- Interrupt handling
-----------------------------------------------------------------------------
-- Sampling the tx_Buffer_Empty signal in order to detect a rising edge
TX_Buffer_Empty_FDRE : FDRE
port map (
Q => tx_Buffer_Empty_Pre, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => '1', -- [in std_logic]
D => tx_Buffer_Empty, -- [in std_logic]
R => write_TX_FIFO); -- [in std_logic]
Interrupt <= enable_interrupts and (rx_Data_Present or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
-----------------------------------------------------------------------------
-- Handling the OPB bus interface
-----------------------------------------------------------------------------
Read_Mux : process (status_reg, OPB_ABus, rx_data) is
begin -- process Read_Mux
mdm_Dbus_i <= (others => '0');
if (OPB_ABus(28 to 29) = STATUS_REG_ADR) then
mdm_Dbus_i(24 to 31) <= status_reg;
else
mdm_Dbus_i(32-C_UART_WIDTH to 31) <= rx_data;
end if;
end process Read_Mux;
Not_All_32_Bits_Are_Used: if (C_UART_WIDTH < 32) generate
MDM_DBus(0 to 31-C_UART_WIDTH) <= (others => '0');
end generate Not_All_32_Bits_Are_Used;
OPB_rdDBus_DFF : for I in 32-C_UART_WIDTH to 31 generate
OPB_rdBus_FDRE : FDRE
port map (
Q => MDM_DBus(I), -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => mdm_CS_2, -- [in std_logic]
D => mdm_Dbus_i(I), -- [in std_logic]
R => xfer_Ack); -- [in std_logic]
end generate OPB_rdDBus_DFF;
-- Generating read and write pulses to the FIFOs
write_TX_FIFO <= mdm_CS_2 and (not OPB_RNW_1) when (OPB_ABus(28 to 29) = TX_FIFO_ADR) else '0';
read_RX_FIFO <= mdm_CS_2 and OPB_RNW_1 when (OPB_ABus(28 to 29) = RX_FIFO_ADR) else '0';
-- No need for duplicate register
--
-- XFER_Control : process (OPB_Clk, OPB_Rst) is
-- begin -- process XFER_Control
-- if OPB_Rst = '1' then -- asynchronous reset (active high)
-- xfer_Ack <= '0';
-- elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
-- xfer_Ack <= mdm_CS_2;
-- end if;
-- end process XFER_Control;
xfer_Ack <= mdm_CS_3;
MDM_xferAck <= xfer_Ack;
-----------------------------------------------------------------------------
-- Instanciating the receive and transmit modules
-----------------------------------------------------------------------------
JTAG_CONTROL_I : JTAG_CONTROL
generic map (
C_MB_DBG_PORTS => C_MB_DBG_PORTS,
C_USE_UART => C_USE_UART,
C_UART_WIDTH => C_UART_WIDTH,
C_USE_FSL => C_USE_FSL, -- [integer]
C_FSL_DATA_SIZE => C_FSL_DATA_SIZE, -- [integer]
C_EN_WIDTH => C_EN_WIDTH
)
port map (
-- Global signals
OPB_Clk => OPB_Clk, -- [in std_logic]
OPB_Rst => OPB_Rst, -- [in std_logic]
Clear_Ext_BRK => clear_Ext_BRK, -- [in std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
Debug_Rst => Debug_Rst, -- [out std_logic]
Read_RX_FIFO => read_RX_FIFO, -- [in std_logic]
Reset_RX_FIFO => reset_RX_FIFO, -- [in std_logic]
RX_Data => rx_Data, -- [out std_logic_vector(0 to 7)]
RX_Data_Present => rx_Data_Present, -- [out std_logic]
RX_BUFFER_FULL => rx_BUFFER_FULL, -- [out std_logic]
Write_TX_FIFO => write_TX_FIFO, -- [in std_logic]
Reset_TX_FIFO => reset_TX_FIFO, -- [in std_logic]
TX_Data => OPB_DBus(32-C_UART_WIDTH to 31), -- [in std_logic_vector(0 to 7)]
TX_Buffer_Full => tx_Buffer_Full, -- [out std_logic]
TX_Buffer_Empty => tx_Buffer_Empty, -- [out std_logic]
-- MDM signals
TDI => TDI, -- [in std_logic]
RESET => RESET, -- [in std_logic]
UPDATE => UPDATE, -- [in std_logic]
SHIFT => SHIFT, -- [in std_logic]
SEL => SEL, -- [in std_logic]
DRCK => DRCK, -- [in std_logic]
TDO => TDO, -- [out std_logic]
-- MicroBlaze Debug Signals
MB_Debug_Enabled => MB_Debug_Enabled, -- [out std_logic_vector(0 to 7)]
Dbg_Clk => Dbg_Clk, -- [out std_logic]
Dbg_TDI => Dbg_TDI, -- [out std_logic]
Dbg_TDO => Dbg_TDO, -- [in std_logic]
Dbg_Reg_En => Dbg_Reg_En, -- [out std_logic_vector(0 to 4)]
Dbg_Capture => Dbg_Capture, -- [out std_logic]
Dbg_Update => Dbg_Update, -- [out std_logic]
FSL0_S_Clk => FSL0_S_Clk,
FSL0_S_Read => FSL0_S_Read,
FSL0_S_Data => FSL0_S_Data,
FSL0_S_Control => FSL0_S_Control,
FSL0_S_Exists => FSL0_S_Exists,
FSL0_M_Clk => FSL0_M_Clk,
FSL0_M_Write => FSL0_M_Write,
FSL0_M_Data => FSL0_M_Data,
FSL0_M_Control => FSL0_M_Control,
FSL0_M_Full => FSL0_M_Full,
jtag_clk => jtag_clk,
trig => trig,
data => data
);
-----------------------------------------------------------------------------
-- Enables for each debug port
-----------------------------------------------------------------------------
Generate_Dbg_Port_Signals : process (MB_Debug_Enabled, Dbg_TDI, Dbg_Reg_En, Dbg_TDO_I,
Dbg_Capture, Dbg_Update) is
variable dbg_tdo_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
-- default values
for I in 0 to 7 loop
Dbg_TDI_I(I) <= '0';
Dbg_Reg_En_I(I) <= "00000";
Dbg_Capture_I(I) <= '0';
Dbg_Update_I(I) <= '0';
end loop; -- I
dbg_tdo_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (MB_Debug_Enabled(I) = '1') then
Dbg_TDI_I(I) <= Dbg_TDI;
Dbg_Reg_En_I(I) <= Dbg_Reg_En;
Dbg_Capture_I(I) <= Dbg_Capture;
Dbg_Update_I(I) <= Dbg_Update;
dbg_tdo_or := dbg_tdo_or or Dbg_TDO_I(I);
end if;
end loop; -- I
Dbg_TDO <= dbg_tdo_or;
end process Generate_Dbg_Port_Signals;
Dbg_Clk_0 <= Dbg_Clk;
Dbg_TDI_0 <= Dbg_TDI_I(0);
Dbg_Reg_En_0 <= Dbg_Reg_En_I(0);
Dbg_Capture_0 <= Dbg_Capture_I(0);
Dbg_Update_0 <= Dbg_Update_I(0);
Dbg_TDO_I(0) <= Dbg_TDO_0;
Dbg_Clk_1 <= Dbg_Clk;
Dbg_TDI_1 <= Dbg_TDI_I(1);
Dbg_Reg_En_1 <= Dbg_Reg_En_I(1);
Dbg_Capture_1 <= Dbg_Capture_I(1);
Dbg_Update_1 <= Dbg_Update_I(1);
Dbg_TDO_I(1) <= Dbg_TDO_1;
Dbg_Clk_2 <= Dbg_Clk;
Dbg_TDI_2 <= Dbg_TDI_I(2);
Dbg_Reg_En_2 <= Dbg_Reg_En_I(2);
Dbg_Capture_2 <= Dbg_Capture_I(2);
Dbg_Update_2 <= Dbg_Update_I(2);
Dbg_TDO_I(2) <= Dbg_TDO_2;
Dbg_Clk_3 <= Dbg_Clk;
Dbg_TDI_3 <= Dbg_TDI_I(3);
Dbg_Reg_En_3 <= Dbg_Reg_En_I(3);
Dbg_Capture_3 <= Dbg_Capture_I(3);
Dbg_Update_3 <= Dbg_Update_I(3);
Dbg_TDO_I(3) <= Dbg_TDO_3;
Dbg_Clk_4 <= Dbg_Clk;
Dbg_TDI_4 <= Dbg_TDI_I(4);
Dbg_Reg_En_4 <= Dbg_Reg_En_I(4);
Dbg_Capture_4 <= Dbg_Capture_I(4);
Dbg_Update_4 <= Dbg_Update_I(4);
Dbg_TDO_I(4) <= Dbg_TDO_4;
Dbg_Clk_5 <= Dbg_Clk;
Dbg_TDI_5 <= Dbg_TDI_I(5);
Dbg_Reg_En_5 <= Dbg_Reg_En_I(5);
Dbg_Capture_5 <= Dbg_Capture_I(5);
Dbg_Update_5 <= Dbg_Update_I(5);
Dbg_TDO_I(5) <= Dbg_TDO_5;
Dbg_Clk_6 <= Dbg_Clk;
Dbg_TDI_6 <= Dbg_TDI_I(6);
Dbg_Reg_En_6 <= Dbg_Reg_En_I(6);
Dbg_Capture_6 <= Dbg_Capture_I(6);
Dbg_Update_6 <= Dbg_Update_I(6);
Dbg_TDO_I(6) <= Dbg_TDO_6;
Dbg_Clk_7 <= Dbg_Clk;
Dbg_TDI_7 <= Dbg_TDI_I(7);
Dbg_Reg_En_7 <= Dbg_Reg_En_I(7);
Dbg_Capture_7 <= Dbg_Capture_I(7);
Dbg_Update_7 <= Dbg_Update_I(7);
Dbg_TDO_I(7) <= Dbg_TDO_7;
end architecture IMP;
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