📄 mdm_core.vhd
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-------------------------------------------------------------------------------
-- $Id: mdm_core.vhd,v 1.1 2004/08/12 01:42:47 khangdao Exp $
-------------------------------------------------------------------------------
-- mdm_core.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mdm_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_core.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2004/08/12 01:42:47 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity MDM_Core is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_USE_FSL : integer := 0;
C_FSL_DATA_SIZE : integer := 32
);
port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
-- OPB signals
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
MDM_DBus : out std_logic_vector(0 to 31);
MDM_errAck : out std_logic;
MDM_retry : out std_logic;
MDM_toutSup : out std_logic;
MDM_xferAck : out std_logic;
-- JTAG signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 4);
Dbg_Capture_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 4);
Dbg_Capture_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 4);
Dbg_Capture_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 4);
Dbg_Capture_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 4);
Dbg_Capture_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 4);
Dbg_Capture_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 4);
Dbg_Capture_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 4);
Dbg_Capture_7 : out std_logic;
Dbg_Update_7 : out std_logic;
FSL0_S_Clk : out std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_Control : in std_logic;
FSL0_S_Exists : in std_logic;
FSL0_M_Clk : out std_logic;
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_Control : out std_logic;
FSL0_M_Full : in std_logic;
jtag_clk : out std_logic;
trig : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0)
);
end entity MDM_Core;
library proc_common_v1_00_c;
use proc_common_v1_00_c.pselect;
library unisim;
use unisim.vcomponents.all;
library opb_mdm_v2_01_a;
use opb_mdm_v2_01_a.all;
architecture IMP of MDM_CORE is
-- component FDR is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDR;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
cs : out std_logic);
end component pselect;
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
component JTAG_CONTROL is
generic (
C_MB_DBG_PORTS : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_USE_FSL : integer := 0;
C_FSL_DATA_SIZE : integer := 32;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_BUFFER_FULL : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(0 to C_EN_WIDTH-1);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 4);
Dbg_Capture : out std_logic;
Dbg_Update : out std_logic;
FSL0_S_Clk : out std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_Control : in std_logic;
FSL0_S_Exists : in std_logic;
FSL0_M_Clk : out std_logic;
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_Control : out std_logic;
FSL0_M_Full : in std_logic;
jtag_clk : out std_logic;
trig : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component JTAG_CONTROL;
-- Returns the minimum value of the two parameters
function IntMin (a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
constant RX_FIFO_ADR : std_logic_vector(0 to 1) := "00";
constant TX_FIFO_ADR : std_logic_vector(0 to 1) := "01";
constant STATUS_REG_ADR : std_logic_vector(0 to 1) := "10";
constant CTRL_REG_ADR : std_logic_vector(0 to 1) := "11";
constant DBUS_START : integer := IntMin( (32 - C_UART_WIDTH), 24 );
-- Read Only
signal status_Reg : std_logic_vector(0 to 7);
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- Write Only
-- Control Register
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4 Dont'Care
-- bit 5 Clear Ext BRK signal
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal clear_Ext_BRK : std_logic;
signal enable_interrupts : std_logic;
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