📄 mdm.vhd
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-------------------------------------------------------------------------------
-- $Id: mdm.vhd,v 1.1 2004/08/12 01:42:47 khangdao Exp $
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2004/08/12 01:42:47 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity OPB_MDM is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_8000";
C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFF_80FF";
C_FAMILY : string := "virtex2";
C_MB_DBG_PORTS : integer := 1;
C_USE_UART : integer := 1;
C_UART_WIDTH : integer := 32;
C_WRITE_FSL_PORTS : integer := 0
);
port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
-- OPB signals
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
MDM_DBus : out std_logic_vector(0 to 31);
MDM_errAck : out std_logic;
MDM_retry : out std_logic;
MDM_toutSup : out std_logic;
MDM_xferAck : out std_logic;
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 4);
Dbg_Capture_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 4);
Dbg_Capture_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 4);
Dbg_Capture_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 4);
Dbg_Capture_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 4);
Dbg_Capture_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 4);
Dbg_Capture_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 4);
Dbg_Capture_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 4);
Dbg_Capture_7 : out std_logic;
Dbg_Update_7 : out std_logic;
-- Connect the BSCAN's USER1 + common signals to the external pins
-- These signals can be connected to an ICON core instantiated by the user
-- Will not be used if the ICON is inserted within the mdm
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
---------------------------------------------------------------------------
-- FSL ports
---------------------------------------------------------------------------
FSL0_S_Clk : out std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Control : in std_logic;
FSL0_S_Exists : in std_logic;
FSL0_M_Clk : out std_logic;
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Control : out std_logic;
FSL0_M_Full : in std_logic
);
end entity OPB_MDM;
library unisim;
use unisim.vcomponents.all;
library opb_mdm_v2_01_a;
use opb_mdm_v2_01_a.all;
library proc_common_v1_00_c;
use proc_common_v1_00_c.family.all;
architecture IMP of OPB_MDM is
constant C_FSL_DATA_SIZE : integer := 32;
attribute BOX_TYPE : string;
-- component BUFG is
-- port (
-- O : out std_logic;
-- I : in std_logic);
-- end component;
component BSCAN_VIRTEX
port
(
TDO1 : in std_logic;
TDO2 : in std_logic;
UPDATE : out std_logic;
SHIFT : out std_logic;
RESET : out std_logic;
TDI : out std_logic;
SEL1 : out std_logic;
DRCK1 : out std_logic;
SEL2 : out std_logic;
DRCK2 : out std_logic
);
end component;
attribute BOX_TYPE of BSCAN_VIRTEX : component is "black_box";
-- component BSCAN_VIRTEX2
-- port
-- (
-- TDO1 : in std_logic;
-- TDO2 : in std_logic;
-- UPDATE : out std_logic;
-- SHIFT : out std_logic;
-- RESET : out std_logic;
-- TDI : out std_logic;
-- SEL1 : out std_logic;
-- DRCK1 : out std_logic;
-- SEL2 : out std_logic;
-- DRCK2 : out std_logic;
-- CAPTURE : out std_logic
-- );
-- end component;
-- attribute BOX_TYPE of BSCAN_VIRTEX2 : component is "black_box";
component BSCAN_VIRTEX4
generic (
JTAG_CHAIN : integer := 1
);
port
(
TDO : in std_logic;
CAPTURE : out std_logic;
DRCK : out std_logic;
RESET : out std_logic;
SEL : out std_logic;
SHIFT : out std_logic;
TDI : out std_logic;
UPDATE : out std_logic
);
end component;
attribute box_type of BSCAN_VIRTEX4: component is "black_box";
component MDM_Core is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_USE_FSL : integer := 0;
C_FSL_DATA_SIZE : integer := 32
);
port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
-- OPB signals
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
MDM_DBus : out std_logic_vector(0 to 31);
MDM_errAck : out std_logic;
MDM_retry : out std_logic;
MDM_toutSup : out std_logic;
MDM_xferAck : out std_logic;
-- JTAG signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
SEL : in std_logic;
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